Whether the IQ modulator is used in a direct conversion application or as an upconverter to the first intermediate frequency (IF), there is usually some gain applied directly after the IQ modulator. This article will describe how to select the appropriate driver amplifier to provide the first stage of gain at the output of the IQ modulator. The devices shown in Figure 1 are  the ADL5375 IQ modulator and ADL5320 driver amplifier. The two devices are well matched on a systemic level; that is, they have equivalent performance, so there is no overall performance degradation from either device. Since the dynamic ranges of these devices are well matched, a simple direct connection between the IQ modulator and the RF driver amplifier is recommended without any attenuation between the devices.

The ADL5375 is a general-purpose, high-performance IQ modulator with an output frequency range from 400 MHz to 6 GHz. Due to its low noise and wide input baseband bandwidth of 750 MHz (3 dB), the device can be driven with signals of a variety of modulations and bandwidths. These input signals can be centered at DC or complex IF.

The LO interface with the ADL5375 is 1XLO type, that is, the output frequency and the LO frequency are equal (when the baseband signal is centered on DC). Circuit Note CN-0134 describes how to drive the ADF4350 through the ADL5375 .

System Level Calculations and RF Amplifier Selection

In the frequency range of 1 GHz to 2 GHz, the output compression point (OP1dB) and third-order compression point (OIP3) of the ADL5375 are approximately 10 dBm and 25 dBm respectively. When selecting an RF amplifier to provide gain after the IQ modulator, you must choose a device with input P1dB and input IP3 equal to or slightly above these values. If the selected device has lower input P1dB and lower input IP3, it will result in reduced cascade performance; if these two specifications are significantly higher than the ADL5375, it will not bring any benefit and may cause the total supply current of the signal chain to increase. No need to increase.

The ADL5320 is a driver amplifier (RF amplifier requiring external tuning components) rated for operation from 400 MHz to 2700 MHz. When powered by a 5 V power supply, its power consumption is 104 mA (it can also be powered by a power supply as low as 3.3 V, in which case power consumption and performance are reduced).

Table 1 shows the output-referred IP3 (OIP3) and P1dB (OP1dB) of the ADL5375 IQ modulator and the input-referred specifications of the ADL5320 driver amplifier at 1900 MHz. In both cases, the difference between the output-referred specifications of the IQ modulator and the input-referred specifications of the amplifier is about 3 dB.

Figure 2 shows the simulated cascade performance of the IQ modulator and driver amplifier at 2140 MHz. This simulation is done using the ADIsimRF design tool . It is worth noting that the 12.3 dB difference between the modulator's OIP3 (24.2 dBm) and the composite OIP3 (36.5 dBm) is just slightly less than the gain of the ADL5320 driver amplifier (13.7 dB). This shows that the driver amplifier has very little impact on the overall OIP3.

Figure 3 shows the measured OIP3 versus output power (POUT) at the output of the IQ modulator and the output of the composite circuit. The shapes of the two OIP3 curve profiles are very similar, and they only deviate in terms of output power and OIP3. This further demonstrates that IP3 only degrades slightly as the signal passes through the RF amplifier.

Select output power level

Although the OIP3 level of the circuit is in the range of 35 dBm to 40 dBm at output power levels up to 15 dBm, this is not achievable in practical operation, especially when the envelope modulation scheme is not constant, as such schemes often have Relatively high peak-to-average ratio. To understand this, examine the circuit's input voltage versus output power transfer function and then consider typical drive levels at the input of an IQ modulator.

Figure 4 shows the circuit transfer function in terms of output power (dBm) and input voltage (V pp) using a CW sine wave drive signal. IQ modulators such as the ADL5375 are typically driven by dual-channel, current-output, digital-to-analog converters (DACs). Typically, the two current outputs of the DAC (nominal range is 0 mA to 20 mA) are connected to ground through two 50Ω resistors, and two 100Ω shunt resistors are placed on each IQ input (more information on this interface For more information, see Circuit Note CN-0205 ). With the DAC operating at 0 dBFS, this corresponds to a drive level on the IQ modulator of 1 V pp or 0.353 V rms (ignoring here the insertion loss of the low-pass filter, which is typically placed between the DAC and IQ modulator between devices). This results in an output power of approximately 13 dBm.

The circuit transfer function represented by

Assuming that the I and Q inputs of the IQ modulator are terminated with 100Ω resistors as described above, the output power can be plotted relative to the dBFS drive level of a typical ADI DAC (see Figure 5). Therefore, a drive level of 0 dBFS corresponds to 1 V pp, which produces the same 13 dBm output power as described above.

Figure 5 also shows the transfer function of the circuit when the I and Q inputs are not terminated with 100 Ω resistors. Since the resulting DAC voltage drive level is doubled (2 Vp-p maximum), the resulting output power is increased by 6 dB relative to the same DAC drive level.

While the circuit can be run without the I and Q termination resistors, this does create some problems for the filter that is typically placed between the DAC and IQ modulator. Since this filter is typically terminated at both ends, it is a good idea to place some resistors between the I and Q inputs of the IQ modulator (the unterminated input resistance of these inputs is about 60 kΩ). Resistor values ​​in the range of 100 Ω to 1000 Ω can be used to increase the resulting DAC voltage drive level and corresponding output power. However, care should be taken when designing the filter between the DAC and the IQ modulator to ensure that it supports different source and load impedances.

As mentioned above, it can be seen from Figure 4 and Figure 5 that the output power is approximately 13 dBm with a 1 V pp sine wave (0dBFS) signal (the I and Q inputs are terminated through 100 Ω resistors). In practice, the DAC drive level must be slightly below 0 dBFS to reduce distortion (typically 1 dB to 2 dB). In addition, the rms drive level should also be reduced by a specific amplitude equal to the peak-to-average ratio of the carrier modulation. The ratio of peak envelope power (PEP) to rms power is typically between 5 dB (for modulation schemes like QPSK and 0 dB in the special case of constant envelope modulation) to 10 dB (for higher order QAM modulation scheme). See Figure 6, which shows that output power levels in the range of 0 dBm to 10 dBm are feasible.

The adjacent channel power ratio (ACPR) of single-carrier wideband code division multiple access (WCDMA) signals has become a mainstream metric for evaluating system-level distortion in circuits (that is, relative to evaluations that rely solely on IP3 and IMD levels). Figure 6 shows the measured relationship between circuit ACPR and output power level. In the case of a WCDMA signal, ACPR is defined as the ratio of the power in the carrier (bandwidth 3.84 MHz) to the power in the adjacent channel (channel spacing of 5 MHz), also measured at a bandwidth of 3.84 MHz. The curve also shows the phase-to-channel power ratio for the same measurement, but with a carrier offset of 10 MHz.

In this example, the ratio of PEP to rms of the signal is approximately 10 dB (the peak-to-average ratio of the WCDMA signal depends on the carrier configuration and loading method). Based on this curve and the desired ACPR level, select an output power level in the range of 0 dBm to 10 dBm. At power levels below 0 dBm, ACPR begins to depend on the circuit's progressively lower signal-to-noise ratio.