| Part Number | Manufacturer | Description | Datasheet |
|---|---|---|---|
| CTM8251AT | Taisko | CAN isolated transceiver 3.3V power supply | download |
| HS-ENG092C | Chengdu Hasion Electronics Co., Ltd. | --- | download |
| USB TO RS232/485/TTL | Waveshare Electronics | --- | download |
| SY C-A4-P2-O4 | SHUNYUANSZ | Differential signal input 4-20mA, output 0-5V, auxiliary power supply 12VDC, SIP7 | download |
| SY 4-20mA-P | SHUNYUANSZ | Input 4-20mA, output 4-20mA, two-wire system | download |
| GWS-M100 | Xiaocheng Technology | --- | download |
| GWC-100 | Xiaocheng Technology | . | download |
| GWC-M100 | Xiaocheng Technology | --- | download |
| GWR-M100 | Xiaocheng Technology | --- | download |
| GWD-M100 | Xiaocheng Technology | --- | download |
| KF8F333-TS28 | ChipON | KF8F333 is a Harvard architecture reduced instruction CPU. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, an 8-bit timer and a 16-bit timer/counter T1, two 8-bit PWM modules, and one 10-bit enhanced PWM module, 1 full-duplex asynchronous communication module, 2 analog comparator modules, 1 8-way capacitive touch module, 1 10-bit 12-channel AD module, 1 operational amplifier module, hardware watchdog and low voltage detection and Low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 4K×16-bit program memory and 128×16-bit BLOCK EEPROM | download |
| KF8F333-SS28 | ChipON | KF8F333 is a Harvard architecture reduced instruction CPU. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, an 8-bit timer and a 16-bit timer/counter T1, two 8-bit PWM modules, and one 10-bit enhanced PWM module, 1 full-duplex asynchronous communication module, 2 analog comparator modules, 1 8-way capacitive touch module, 1 10-bit 12-channel AD module, 1 operational amplifier module, hardware watchdog and low voltage detection and Low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 4K×16-bit program memory and 128×16-bit BLOCK EEPROM | download |
| KF8F333-S28 | ChipON | KF8F333 is a Harvard architecture reduced instruction CPU. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, an 8-bit timer and a 16-bit timer/counter T1, two 8-bit PWM modules, and one 10-bit enhanced PWM module, 1 full-duplex asynchronous communication module, 2 analog comparator modules, 1 8-way capacitive touch module, 1 10-bit 12-channel AD module, 1 operational amplifier module, hardware watchdog and low voltage detection and Low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 4K×16-bit program memory and 128×16-bit BLOCK EEPROM | download |
| KF8F312M4-SS20 | ChipON | KF8F312M4 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312M4-S20 | ChipON | KF8F312M4 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312M4-S14 | ChipON | KF8F312M4 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312M4-S8 | ChipON | KF8F312M4 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-TS20 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-SS20 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-S8 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-S20 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-S14 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F212-S8-5 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-S8 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-SS20-5 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-SS20 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-S20-5 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-S20 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-S14-5 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| CSU8RP1381 | Chipsea Technologies | The CSU8RP1381D chip is an 8-bit RISC architecture high-performance microcontroller that integrates an 18-bit high-precision ADC and LCD display module. The peripheral devices of common measurement systems only require 7 ordinary capacitors. This chip enables any system calibration data to be saved in OTP within the range of operating voltage (2.5~3.6V). With UART communication port. | download |
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