AG576SL100 datasheet, PDF - EEWORLD Datasheet

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AG576SL100: CategoryThe embedded processor and controller CPLD/FPGA; File Size284KB，17 Pages; ManufacturerAGM Micro; Websitehttp://www.alta-gate.com; Shanghai AGM Microelectronics Co., Ltd. (AGM) was established in 2012. It is a leading semiconductor integrated circuit fabless design company in China that provides SoC chips for the application market based on programmable logic technology. It was founded by a team from a well-known programmable logic SoC company in Silicon Valley, USA, and a senior domestic engineering team. AGM independently develops and mass-produces domestic programmable logic SoC product series for industrial, consumer, and artificial intelligence application SoC markets. It has certifications from OEMs, customers, and partners, and has independent intellectual property rights in its own compilation software and circuits.

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AGM – CPLD

AGM CPLD

DATASHEET

AGM – CPLD

1. AGM Architecture Overview

1.1. Functional Description

The AGM CPLD devices contain an industrial state-of-the art two-dimensional row- and column-based architecture to

implement custom logic. Column and row interconnects of varies speeds provide signal interconnects between logic blocks

(LBs) and IOs.

The logic array consists of LBs, with 16 logic slices (LS) in each LB. A slice is a small unit of logic providing efficient

implementation of user logic functions. LBs are grouped into rows and columns across the device. The CPLD devices’

density range is up to 576 slices.

The device global clock network consists of up to 4 global clock lines that drive through the entire device. The global clock

network can provide clocks for all resources within the device, such as input/output elements (IOEs), slices. The global

clock lines can also be used for other high fan-out signals.

Each device I/O pin is fed by an IOE located at the ends of LBrows and columns around the periphery of the device. I/O

pins support various single-ended standards. Each IOE contains a bidirectional I/O buffer.

Each device is embedded with a flash memory block. The big portion of this flash memory storage is used as dedicated

configuration flash memory (CFM) block. The CFM flash memory block provides the non-volatile storage for the all SRAM

configuration bits. The CFM automatically downloads and configures the logic blocks and IP during power-on, providing

instant-on sequence operation.

AGM CPLD device partitions 256k bits of flash memory as UFM (user flash memory) as general storage purposes. The

UFM provides programmable port connections to the logic array for reading and writing.

1.2. Logic Array Blocks

Each Logic Block consists of 16 slices, SLICE carry chains, SLICE control signals, a local interconnect, a look-up table

(LUT) chain, and register chain connection lines.

1.3. Logic Element

The smallest unit of logic in AGM architecture, the slice, is compact and provides advanced and flexible features with

efficient logic utilization. Each slice features:



A four-input look-up table (LUT4), which is a function generator that can implement any combinatorial logic function of

four inputs.



A programmable register

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