ASDL-7021
IrDA FIR/VFIR Controller in TFBGA Package
Data Sheet
Description
The ASDL-7021 is a new generation large scale integra-
tion (LSI) IrDA controller supporting speeds of SIR (up
to 115Kbps), MIR(1.152Mbps), FIR(4Mbps) and VFIR
(16Mbps). It consists of IrDA Control Block, Remote
Control Block, Timer Control Block, Global Control block
including Buffer Memory and Direct Memory Access
Control Block (DMA) integrated into one single chip.
It has all the hardware including Buffer Memory and
Direct Memory Access (DMA) that enables convenient
access to its peripheral IO and memories from system bus
which is similar to simple memory devices. ASDL-7021 is
a class of its own as unlike conventional LSI which utilizes
external DMA for implementing fast infrared transfer,
complicated bus timing and required additional logic for
its interface.
ASDL-7021 utilizes two memory banks for external access
and internal DMA access; these 2 banks are interchange-
able to prevent bus contention. These two banks can be
switched using memory select function of the internal
register and separates internal bus from external, which
enables parallel operation of external microcontroller
operation and internal IrDA data transfer operation.
ASDL-7021 has embedded Universal Remote Control (RC)
function for general purpose remote control communica-
tion.
Together with Lite-On FIR transceiver and IrSimple
software, ASDL-7021 is designed to provide Industry
a total solution for high speed wireless connectivity
solution in miniature packaging.
Features
General Features
•
Interfaces with IrDA Compliant IR Transceiver
up to VFIR
•
Miniature 48 pin TFBGA Package
Height : 1.2 mm
Width : 4.0 mm
Depth : 4.0 mm
•
8-bit Memory Mapped Interface
•
Input clock of 48 MHz
•
4 transmission speed in 3 Blocks
- SIR Block (2.4 to 115.2Kbps)
- FIR Block (1.152Mbps for MIR and 4Mbps for FIR)
- VFIR Block (16Mbps)
•
Operating temperature from -40° C ~ 85°C
- Critical parameters are guaranteed over
temperature and supply voltage
•
Core Power Supply = 1.8V
Clock Power Supply = 3.3V
IO Power Supply =1.8V, 2.5V, 3.3V
•
RAM Block with On-Chip buffer memory of 8KByte x 2
Bank Configuration
- 1 bank for external access x 8 bit width
- 1 bank for internal access x 8 bit width through
on-chip DMA block
- These 2 banks can be switched
- Each transmit and receive have their own buffer
memory of 8KByte x 2
BANK0
FIR block
CPU
BANK1
DMA
DMA
FIR block
CPU
BANK1
Applications
•
Mobile Data Communication and Universal Remote
Control
- Mobile Phones
- PDAs
- Digital Still Camera
- Printer
- Notebooks
- Handy Terminal
- Dongles
- Industrial and Medical Instrument
Features (Cont.)
•
Infrared Interface Block
- IrDA send/receive functions (IRTX0, IRRX0)
- Remote Control send function (IRTX1)
•
DMA Block
- DMA transfer function between buffer memory and
SIR, FIR, VFIR block
V IO3
B1
D6
•
Remote Control Block
Generate Remote Control burst signal
•
Timer Block
- 2 channels of generic 16 bit timer
- 1 channel of Mediabusy timer
•
Moisture Level 3
•
Lead-Free and ROHS Compliant
VDDK
VDDK
V IO2
E4
VIO1
F5
V IO1
C2
VDDC
C4
A[7:0]
D[7:0]
C5
VDDK
C6
A6
B6
IrRXD0
IrTX0 (IrDA)
IrTX1 (Remote)
IrOUT0 (IrMode)
Ir0UT1 (SD)
IrDA
Transceiver
I/F
D1,D2,E2,E1,G1,G2,F1,F2
G3,F3,F4,G4,G5,F7,G6,G7
C7
B7
A7
/CS
Host
I/F
/WE
/OE
/IRQ
/SD
/RESET
F6
E5
E6
D7
ASDL-7021
A3
A2
B2
C1
A1
B3
C3
D3
E3
/XTALIN
/XTALOUT
CLKIN
CLKSEL
INTERNAL
CLOCK
EXTERNAL
CLOCK
E7
D5
GND
GND
GND
GND
GND
Figure 1a. Pin Layout of ASDL-7021
Figure 1b. Pin layout of ASDL-7021 (Top View)
Application Support Information
The Application Engineering Group is available to assist you with the application design associated with ASDL-7021
FIR/VFIR Controller. You can contact them through your local sales representatives for additional details.
Order Information
Part Number
ASDL-70
Packaging Type
Tape and Reel
Quantity
4000
I/O Pins Configuration Table
Pins Description
Symbol
Power
VDDK
VDDC
VIO
VIO
VIO
GND
C4,C5,C6
C
E4,F5
D6
B
A,B,C,D,E
POWER
POWER
POWER
POWER
POWER
POWER
.8V Power
.V Power
.8V, .5V, .V
.8V, .5V, .V
.8V, .5V, .V
GND
Pin(s)
Type
Buffer Type
(Refer to Figure 2)
Description
Bus Interface Signals (VIO1 Voltage)
A0-A7
D,D,E,E,
G,G,F,F
G,F,F4,G4
G5,F7,G6,G7
F6
E5
I
I
An 8-bit address signal line connects itself directly with an external address bus. It selects the
internal buffer memory and the register addresses of each function module. With the assertion
of the CS signal, A0 - A7 turn out to be valid, which decides the internal addresses.
An 8-bit data signal line connects itself directly with an external data bus. It is a signal that
performs data conversion with the internal buffer memory and each function module.The bus
direction is determined by WE and OE.
CS is a chip select signal for the IC. Asserting CS activates the external bus of this LSI.
The WE signal turns the direction of a data bus to the input direction, and takes it into the IC for
the internal buffer memory and registers designated by the address bus, at the start-up of the
signal.
The OE signal turns the data bus direction to the output direction, and outputs to the data bus
the contents of the internal buffer memory and register designated by the address bus.
This is a signal line that notifies to the outside that ASDL-70 requests an interrupt.
D0-D7
I/O
IO4
/CS
/WE
I
I
I
I
/OE
/IRQ
E6
D7
I
O
I
O4
Other Signals (VIO1 Voltage)
/RESET
/SD
D5
E7
I
I
I
I (internal PullDown)
This RESET signal resets ASDL-70.
. Low: Shutdown
IC is suspending the clock supply to the core.
The output signal retains the condition.
. High: IC is keeping the clock supply to the core.
However, when the externally connected quartz crystal is used with
CLKSEL=Low, the oscillation of the quartz crystal is kept performed
under the condition of CLKSEL=Low, and SD: Low.
When you want to stop the quartz crystal oscillation, you must set
CLKSEL=High.
. After wake up from SD, the IC must be reset.
This is used for selecting whether the input signal from CLKIN should be used for the
clock input or whether the quartz crystal should be used at XTALIN and XTALOUT.
Using quartz crystal,
CLKSEL = Low, external quartz crystal is kept under oscillation
CLKSEL = High, external quartz crystal is suspending oscillation
Using CLKIN signal, set CLKSEL = High
CLKSEL
C
I
I
Infrared Interface Signal (VIO2 voltage)
IrTXD0
IrTXD
IrRXD0
IrOUT0
IrOUT
B6
C7
A6
B7
A7
O
O
I
O
O
O4
O4
I
O4
O4
This outputs the IrDA infrared signal and remote control send signal.
This outputs the IrDA infrared signal and remote control send signal.
This inputs a signal from the infrared module.
This is an output signal for controlling the infrared module.
This is an output signal for controlling the infrared module.
Clock Signal (VIO3 voltage)
CLKIN
B
I
I
Clock input
Clock Signal (VDDC Voltage)
/XTALIN
A
I
You must connect quartz crystal to create a basic clock or input the clock from outside.
Usually you must connect the quartz crystal between XTALIN and
XTALOUT. The oscillation frequency of the crystal must be 48MHz.
/XTALOUT
A
O
TEST Signal
TEST
TEST
TEST
TESTSE
B5
A5
A4
B4
I
I
I
I
I (Internal PullDown)
I (Internal PullDown)
I (Internal PullDown)
I (Internal PullDown)
Test signal (Set to N.C).
Test signal (Set to N.C).
Test signal (Set to N.C).
Test signal (Set to N.C).
4
Output BufferType
I
VIO
I(pulldown)
VIO
I(schmitt)
VIO
O4:
IOL=4mA,IOH=4mA(VIO = 3.3V)
IOL=2.2mA,IOH=2.2mA(VIO = 2.5V)
IOL=1.4mA,IOH=1.4mA(VIO = 1.8V)
O4
VIO
IO4
VIO
Figure 2. I/O Description
Block Diagram
Figure 3. Block Diagram of internal blocks of ASDL-7021
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