EH2A111-RO datasheet, PDF - EEWORLD Datasheet

EH2A111-RO: DescriptionCard Edge Connector, 202 Contact(s), 2 Row(s), Female, Straight, Surface Mount Terminal, Receptacle; CategoryThe connector The connector; File Size1MB，26 Pages; ManufacturerFOXCONN; Websitehttp://www.fit-foxconn.com/

Download Datasheet Parametric View All

EH2A111-RO Overview

Card Edge Connector, 202 Contact(s), 2 Row(s), Female, Straight, Surface Mount Terminal, Receptacle

Parameter Name	Attribute value
Reach Compliance Code	unknown
Other features	STRADDLE MOUNT
Body/casing type	RECEPTACLE
Connector type	CARD EDGE CONNECTOR
Contact completed and terminated	GOLD FLASH
Contact point gender	FEMALE
DIN compliance	NO
Filter function	NO
IEC compliance	NO
JESD-609 code	e4
MIL compliance	NO
Mixed contacts	NO
Installation method	STRAIGHT
Installation type	BOARD
Number of rows loaded	2
Options	GENERAL PURPOSE
Terminal pitch	1.27 mm
Termination type	SURFACE MOUNT
Total number of contacts	202
UL Flammability Code	94V-0
Base Number Matches	1

The problem of Android emulator's navigation keys not working well: The navigation keys, up, down, left, right and confirmation keys on my Android emulator do not respond. Does anyone know what the problem is? Is it because the version is too high and not supported? I...; chenbingjy Linux and Android

Switching Power Supply Design (Third Edition) PDF scan, 540 pages: ...; buildele Power technology

First meeting: I am very happy to share the joy of learning embedded systems with you....; ljm945 Talking about work

Questions about data conversion: [table=98%,rgb(209, 217, 226)] [tr][td] [/td][td]DBH[/td][td]DBL[/td][/tr] [tr][td]Before conversion[/td][td]0 0 0 0 D11 D10 D9 D8[/td][td]D7 D6 D5 D4 D3 D2 D1 D0[/td][/tr] [tr][td]After conversion[/t...; 功夫佬 51mcu

FPGA-based SATA controller.doc: FPGA-based SATA controller.doc...; zxopenljx FPGA/CPLD

EDA experiment and practice dac_test: module dac_test(clock,key,wr_act,wr_data,seg,dig); input clock; //system clock (48MHz) input[4:0] key; //key input (KEY1~KEY5) output wr_act; //data enable output[10:0]wr_data; //data to be sent outpu...; 白丁 FPGA/CPLD

Popular Components