2SC3311AS datasheet, PDF - EEWORLD Datasheet

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2SC3311AS: DescriptionTransistor; CategoryDiscrete semiconductor The transistor; File Size111KB，1 Pages; ManufacturerJCET; Websitehttp://www.cj-elec.com/; Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

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2SC3311AS Overview

Transistor

2SC3311AS Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknow
Base Number Matches	1

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD

TO-92S Plastic-Encapsulate Transistors

TO – 92S

2SC3311A

TRANSISTOR (NPN)

1. EMITTER

FEATURES

Optimum for High-density Mounting

Allowing Supply with the Radial Taping

Complementary to 2SA1309A

MAXIMUM RATINGS (T

=25℃ unless otherwise noted)

Symbol

CBO

CEO

EBO

θJA

stg

Parameter

Collector-Base Voltage

Collector-Emitter Voltage

Emitter-Base Voltage

Collector Current

Collector Power Dissipation

Thermal Resistance From Junction To Ambient

Junction Temperature

Storage Temperature

Value

0.1

300

417

150

-55~+150

2. COLLECTOR

3. BASE

Unit

℃/W

℃

ELECTRICAL CHARACTERISTICS (T

=25℃ unless otherwise specified)

Parameter

Collector-base breakdown voltage

Collector-emitter breakdown voltage

Emitter-base breakdown voltage

Collector cut-off current

Emitter cut-off current

DC current gain

Collector-emitter saturation voltage

Collector output capacitance

Transition frequency

Symbol

(BR)CBO

(BR)CEO

(BR)EBO

CBO

CEO

EBO

CE(sat)

Test

conditions

Min

0.1

160

3.5

150

460

0.3

MHz

Typ

Max

Unit

μA

= 0.01mA,I

=2mA,I

=0.01mA,I

=10V,I

=7V,I

=10V, I

=2mA

=100mA,I

=10mA

=10V,I

=0, f=1MHz

=10V,I

=2mA, f=200MHz

CLASSIFICATION OF h

RANK

RANGE

160-260

210-340

290-460

A,Dec,2010

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