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Datasheet> All Categories > storage> storage> NT5DS16M16BF-5T
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NT5DS16M16BF-5T

Description
DDR DRAM, 16MX16, 0.65ns, CMOS, PBGA60, CSP-60
Categorystorage    storage   
File Size1MB，80 Pages
ManufacturerNanya
Websitehttp://www.nanya.com/cn
Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.
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NT5DS16M16BF-5T Overview

DDR DRAM, 16MX16, 0.65ns, CMOS, PBGA60, CSP-60

NT5DS16M16BF-5T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerNanya
Parts packaging codeBGA
package instructionBGA, BGA60,9X12,40/32
Contacts60
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.65 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
interleaved burst length2,4,8
JESD-30 codeR-PBGA-B60
length13 mm
memory density268435456 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals60
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA60,9X12,40/32
Package shapeRECTANGULAR
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.6 V
Certification statusNot Qualified
refresh cycle8192
self refreshYES
Continuous burst length2,4,8
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.5 V
Nominal supply voltage (Vsup)2.6 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width8 mm

NT5DS16M16BF-5T Preview

NT5DS64M4BT NT5DS64M4BF
NT5DS32M8BT NT5DS32M8BF
NT5DS16M16BT NT5DS16M16BF
256Mb DDR SDRAM
Features
CAS Latency and Frequency
CAS
Latency
3
2.5
Maximum Operating Frequency (MHz)
DDR400A
DDR400B
(-5)
(-5T)
200
200
200
166
•
•
•
•
•
•
•
•
•
•
•
•
•
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Burst lengths: 2, 4, or 8
CAS Latency: 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8µs Maximum Average Periodic Refresh Interval
SSTL_2 compatible I/O interface
V
DDQ
= 2.6V
±
0.1V
V
DD
= 2.6V
±
0.1V
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456 bits. It is
internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a
2n
prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single
2n-bit
wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode
of operation.
REV 1.1
04/2003
1
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NT5DS64M4BT NT5DS64M4BF
NT5DS32M8BT NT5DS32M8BF
NT5DS16M16BT NT5DS16M16BF
256Mb DDR SDRAM
Pin Configuration - 400mil TSOP II (x4 / x8 / x16)
V
D D
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
NC
V
DDQ
NC
NC
V
D D
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
D D
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
NC
V
DDQ
LDQS
NC
V
DD
NU
LDM*
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
66-pin Plastic TSOP-II 400mil
16Mb x 16
32Mb x 8
64Mb x 4
Column Address Table
Organization
64Mb x 4
32Mb x 8
16Mb x 16
Column Address
A0-A9, A11
A0-A9
A0-A8
*DM is internally loaded to match DQ and DQS identically
.
REV 1.1
04/2003
2
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NT5DS64M4BT NT5DS64M4BF
NT5DS32M8BT NT5DS32M8BF
NT5DS16M16BT NT5DS16M16BF
256Mb DDR SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
64 X 4
1
VSSQ
NC
NC
NC
NC
VREF
2
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ3
NC
DQ2
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ0
NC
DQ1
QFC
NC
WE
RAS
BA1
A0
A2
VDD
8
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
32 X 8
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ6
DQ5
DQ4
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ1
DQ2
DQ3
QFC
NC
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
REV 1.1
04/2003
3
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NT5DS64M4BT NT5DS64M4BF
NT5DS32M8BT NT5DS32M8BF
NT5DS16M16BT NT5DS16M16BF
256Mb DDR SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
16 X 16
1
VSSQ
DQ14
DQ12
DQ10
DQ8
VREF
2
DQ15
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ13
DQ11
DQ9
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ2
DQ4
DQ6
LDQS
LDW
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
REV 1.1
04/2003
4
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NT5DS64M4BT NT5DS64M4BF
NT5DS32M8BT NT5DS32M8BF
NT5DS16M16BT NT5DS16M16BF
256Mb DDR SDRAM
Input/Output Functional Description
Symbol
CK, CK
Type
Input
Function
Clock:
CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self
Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might
include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control
of stacked devices.
Chip Select:
All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in
addition to CS0, to allow upper or lower deck selection on stacked devices.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-
ing a Read, DM can be driven high, low, or floated.
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
Data Input/Output:
Data bus.
Data Strobe:
Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-
DQ7; UDQS corresponds to the data on DQ8-DQ15
No Connect:
No internal electrical connection is present.
Electrical connection is present. Should not be connected at second level of assembly.
Supply
Supply
Supply
Supply
Supply
DQ Power Supply:
2.6V
±
0.1V.
DQ Ground
Power Supply:
2.6V
±
0.1V.
Ground
SSTL_2 reference voltage:
(V
DDQ
/ 2)
±
1%.
CKE, CKE0, CKE1
Input
CS, CS0, CS1
Input
RAS, CAS , WE
Input
DM
Input
BA0, BA1
Input
A0 - A12
Input
DQ
DQS, LDQS, UDQS
NC
NU
V
DDQ
V
SSQ
V
DD
V
SS
V
REF
Input/Output
Input/Output
REV 1.1
04/2003
5
©
NANYA TECHNOLOGY CORP
. All rights reserved.
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