UT61L1024SCL-12E datasheet, PDF

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UT61L1024SCL-12E: DescriptionStandard SRAM, 128KX8, 12ns, CMOS, PDSO32; Categorystorage storage; File Size112KB，14 Pages; ManufacturerUTRON; Websitehttp://www.utron.net/; Utron Technologies Corp. was established in 1983, specializing in the design and manufacture of bare board and cable testers. We are a well-known manufacturer and exporter of PCB and cable testers for over 14 years.

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UT61L1024SCL-12E Overview

Standard SRAM, 128KX8, 12ns, CMOS, PDSO32

UT61L1024SCL-12E Parametric

Parameter Name	Attribute value
Maker	UTRON
package instruction	SOP, SOP32,.56
Reach Compliance Code	unknown
Maximum access time	12 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G32
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	80 °C
Minimum operating temperature	-20 °C
organize	128KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP32,.56
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
power supply	3.3 V
Certification status	Not Qualified
Maximum standby current	0.003 A
Minimum standby current	2 V
Maximum slew rate	0.1 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL

UT61L1024SCL-12E Preview



UTRON

Rev 1.1

UT61L1024(E)

128K X 8 BIT HIGH SPEED CMOS SRAM

REVISION HISTORY

REVISION

Rev. 1.0

Rev. 1.1

DESCRIPTION

Original.

1.Add order information for lead free product

2.Revised timing read/write waveform

3.Add *V

=-3.0V for pulse width less than 10ns into DC table

Draft Date

Nov. 06 2002

May. 22 2003

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

P80040



UTRON

Rev 1.1

UT61L1024(E)

128K X 8 BIT HIGH SPEED CMOS SRAM

GENERAL DESCRIPTION

The UT61L1024(E) is a 1,048,576-bit high-speed

CMOS static random access memory organized

as 131,072 words by 8 bits. It is fabricated using

high performance, high reliability CMOS

technology.

The UT61L1024(E) is designed for high-speed

system applications. It is particularly suited for use

in high-density high-speed system applications.

The UT61L1024(E) operates from a single 3.3V

power supply and all inputs and outputs are fully

TTL compatible.

FEATURES

Fast access time : 12/15ns (max.)

Low power operating : 60mA (typ.)

Single 3.0V~3.6V power supply

Operating temperature :

Extended : -20

℃

~80

℃

All inputs and outputs TTL compatible

Fully static operation

Three state outputs

Data retention voltage : 2V (min.)

Package : 32-pin 300 mil skinny PDIP

32-pin 300 mil SOJ

32-pin 450mil SOP

32-pin 8mm x 20mm TSOP-1

32-pin 8mm x 13.4mm STSOP

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

A16

Vcc

A15

CE2

A0-A16

DECODER

2048 X 512

MEMORY

ARRAY

A14

A12

UT61L1024(E)

A13

A11

Vcc

Vss

I/O1-I/O8

I/O DATA

CIRCUIT

COLUMN I/O

I/O1

I/O2

I/O3

A10

I/O8

I/O7

I/O6

I/O5

I/O4

CE2

Vss

CONTROL

CIRCUIT

PDIP / SOJ/SOP

PIN DESCRIPTION

SYMBOL

A0 - A16

I/O1 - I/O8

CE ,CE2

DESCRIPTION

Address Inputs

Data Inputs/Outputs

Chip enable 1,2 Inputs

Write Enable Input

Output Enable Input

Power Supply

Ground

No Connection

A11

A13

CE2

A15

Vcc

A16

A14

A12

A10

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

UT61L1024(E)

TSOP-I/STSOP

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

P80040



UTRON

Rev 1.1

UT61L1024(E)

128K X 8 BIT HIGH SPEED CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Terminal Voltage with Respect to Vss

Operating Temperature

Storage Temperature

Power Dissipation

DC Output Current

Soldering Temperature (under 10 sec)

SYMBOL

TERM

STG

OUT

Tsolder

RATING

-0.5 to 4.6

-20 to 80

-65 to 150

260

UNIT

℃

*Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect

device reliability.

TRUTH TABLE

MODE

Standby

Output Disable

Read

Write

Note:

CE2

I/O OPERATION

High - Z

High -Z

High - Z

OUT

SUPPLY CURRENT

SB1

H = V

, L=V

, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

= 3.0V

∼

3.6V, T

= -20

℃

to 80

℃

)

PARAMETER

Power Voltage

Input High Voltage

Input Low Voltage

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

Operating Power

Supply Current

Standby Power

Supply Current

SB1

SYMBOL

Vcc

TEST CONDITION

MIN.

3.0

2.0

- 0.5

-1

2.2

MAX.

3.6

+0.5

0.6

0.4

100

UNIT

µA

≦

I/O

≦

CE = V

or CE2 = V

= V

= - 4mA

= 8mA

Cycle time=Min, I

I/O

= 0mA

. CE = V

, CE2 = V

CE = V

or CE2 = V

≧

-0.2V ;or CE2

≦

0.2V

- 12

- 15

Notes:

1. Overshoot : Vcc+3.0v for pulse width less than 8ns.

2. Undershoot : Vss-3.0v for pulse width less than 8ns.

3. Overshoot and Undershoot are sampled, not 100% tested.

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

P80040



UTRON

Rev 1.1

UT61L1024(E)

128K X 8 BIT HIGH SPEED CMOS SRAM

SYMBOL

I/O

MIN.

MAX.

UNIT

CAPACITANCE

=25

℃

, f=1.0MHz)

PARAMETER

Input Capacitance

Input/Output Capacitance

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Reference Levels

Output Load

0V to 3.0V

3ns

1.5V

=30pF, I

=-4mA/8mA

AC ELECTRICAL CHARACTERISTICS

= 3.0V

∼

3.6V , T

= -20

℃

to 80

℃

)

(1) READ CYCLE

PARAMETER

Read Cycle Time

Address Access Time

Chip Enable Access Time

Output Enable Access Time

Chip Enable to Output in Low Z

Output Enable to Output in Low Z

Chip Disable to Output in High Z

Output Disable to Output in High Z

Output Hold from Address Change

(2) WRITE CYCLE

PARAMETER

Write Cycle Time

Address Valid to End of Write

Chip Enable to End of Write

Address Set-up Time

Write Pulse Width

Write Recovery Time

Data to Write Time Overlap

Data Hold from End of Write Time

Output Active from End of Write

Write to Output in High Z

SYMBOL

CW1

, t

CW2

OW*

WHZ*

UT61L1024-12 UT61L1024-15

MIN.

MAX. MIN.

MAX.

UNIT

SYMBOL

ACE1

, t

ACE1

CLZ1*

, t

CLZ2*

OLZ*

CHZ1*

, t

CHZ2*

OHZ*

UT61L1024-12 UT61L1024-15

MIN.

MAX. MIN.

MAX.

UNIT

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

P80040



UTRON

Rev 1.1

UT61L1024(E)

128K X 8 BIT HIGH SPEED CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2)

Address

Dout

Previous data valid

Data Valid

READ CYCLE 2

(

and

CE2

and

Controlled)

(1,3,4,5)

Address

ACE

CE2

CLZ

OLZ

Dout

High-Z

Data Valid

CHZ

OHZ

High-Z

Notes :

is high for read cycle.

2.Device is continuously selected OE =low, CE =low

CE2=high

3.Address must be valid prior to or coincident with CE =low

CE2=high; otherwise t

is the limiting parameter.

4.t

CLZ

, t

OLZ

, t

CHZ

and t

OHZ

are specified with C

=5pF. Transition is measured±500mV from steady state.

5.At any given temperature and voltage condition, t

CHZ

is less than t

CLZ

, t

OHZ

is less than t

OLZ

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

P80040

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