2N7002KW
60V N-Channel Enhancement Mode MOSFET - ESD Protected
FEATURES
• R
DS(ON)
, V
GS
@10V,I
DS
@500mA=3Ω
• R
DS(ON)
, V
GS
@4.5V,I
DS
@200mA=4Ω
• Advanced Trench Process Technology
• High Density Cell Design For Ultra Low On-Resistance
• Very Low Leakage Current In Off Condition
• Specially Designed for Battery Operated Systems, Solid-State Relays
Drivers : Relays, Displays, Lamps, Solenoids, Memories, etc.
• ESD Protected 2KV HBM
• Lead free in compliance with EU RoHS 2011/65/EU directive
• Green molding compound as per IEC61249 Std. . (Halogen Free)
008
0
MECHANICAL DATA
• Case: SOT-323 Package
• Terminals: Solderable per MIL-ST
D-750,Method 2026
• Approx weight: 0.0002 ounce, 0.005 gram
• Marking: K72
Maximum RATINGS and Thermal Characteristics (T
A
=25
O
C unless otherwise noted )
PA RA M E TE R
D r a i n- S o ur c e Vo lta g e
Ga te - S o ur c e Vo lta g e
C o nti nuo us D r a i n C ur r e nt
P uls e d D r a i n C ur r e nt
1)
S ym b o l
V
DS
V
GS
I
D
I
D M
T
A
= 2 5
O
C
T
A
= 7 5
O
C
P
D
T
J
,T
S TG
R
θJ
A
Li mi t
60
+20
11 5
800
200
120
-55 t o + 1 50
625
Uni ts
V
V
mA
mA
mW
O
M a xi m um P o we r D i s s i p a ti o n
Op e r a ti ng J unc ti o n a nd S to r a g e
Te mp e r a tur e Ra ng e
Junction-to Ambient Thermal
Resistance(PCB mounted)
2
C
O
C /W
Note:1.Maximum DC current limited by the package
2.Surface mounted on FR4 board, t < 10 sec
3.Pulse width<300us, Duty cycle<2%
May 13,2015-REV.02
PAGE . 1
2N7002KW
ELECTRICALCHARACTERISTICS
P a ra me te r
S ta ti c
D ra i n-S o urc e B re a k d o wn
Vo lta g e
G a te Thr e s ho ld Vo lta g e
D ra i n-S o urc e O n-S ta te
Re s i s ta nc e
D ra i n-S o urc e O n-S ta te
Re s i s ta nc e
Ze r o G a te V o lta g e D ra i n
C ur re nt
Gate Body Leakage
Forward Transconductance
Dynamic
To ta l G a te C ha r g e
Tur n- On D e la y Ti m e
Tur n- Off D e la y Ti m e
Inp ut C a p a c i ta nc e
O utp ut C a p a c i ta nc e
Re ve r s e Tra ns fe r
C a p a c i ta nc e
S o urc e - D r a i n D i o d e
D i o d e F o rwa r d Vo lta g e
C o nti nuo us D i o d e F o r wa r d
C ur re nt
P uls e d D i o d e F o r wa rd
C ur re nt
V
SD
I
s
I
s M
I
S
= 2 0 0 mA , V
GS
= 0 V
-
-
-
-
-
0 .8 2
-
-
1 .3
11 5
800
V
mA
mA
Q
g
t
on
t
off
C
iss
C
oss
C
rss
V
D S
= 2 5 V, V
GS
=0 V
f=1 .0 M H
Z
V
D S
= 1 5 V, I
D
= 2 0 0 m A
V
GS
=4.5V
V
DD
=30V , R
L
=150Ω
I
D
=200mA , V
GEN
=10V
R
G
=10Ω
-
-
-
-
-
-
-
-
-
-
-
-
0 .8
20
40
35
10
5
pF
nC
B V
DSS
V
GS ( th)
R
D S ( o n)
R
D S ( o n)
I
D S S
I
GS S
g
fS
V
GS
= 0 V, I
D
=1 0 uA
V
D S
=V
GS
, I
D
=2 5 0 uA
V
GS
=4.5V, I
D
=200mA
V
GS
=10V, I
D
=500mA
V
DS
=60V, V
GS
=0V
V
GS
= +2 0 V, V
D S
=0 V
V
D S
= 1 5 V, I
D
= 2 5 0 m A
60
1
-
-
-
-
100
-
-
-
-
-
-
-
-
2 .5
4 .0
3.0
1
+1 0
-
Ω
V
V
S ym b o l
Te s t C o nd i ti o n
M i n.
Typ .
M a x.
Uni ts
uA
uA
mS
ns
Switching
Test Circuit
V
IN
V
DD
R
L
V
OUT
Gate Charge
Test Circuit
V
GS
V
DD
R
L
R
G
1mA
R
G
May 13,2015-REV.02
PAGE . 2
2N7002KW
Vgs
Qg
V
GS
- Gate-to-Source Voltage (V)
10
8
6
4
2
0
V
DS
=10V
I
D
=250mA
Vgs(th)
Qg(th)
Qgs
Qsw
0
0.2
0.4
0.6
0.8
1
Qgd
Qg
Q
g
- Gate Charge (nC)
Fig.6 - Gate Charge Waveform
V
th
- G-S Threshold Voltage (NORMALIZED)
Fig.7 - Gate Charge
88
86
84
82
80
78
76
74
72
-50
I
D
=250mA
1.1
1
0.9
0.8
0.7
-50
BV
DSS
- Breakdown Voltage (V)
150
1.2
ID = 250uA
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
150
T
J
- Junction Temperature (
o
C)
T
J
- Junction Temperature (
o
C)
Fig.8 - Threshold Voltage vs Temperature
Fig.9 - Breakdown Voltage vs Junction Temperature
10
V
GS
=0V
I
S
- Source Current (A)
1
0.1
T
J
=125
℃
25
℃
-55
℃
0.01
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
V
SD
- Source-to-Drain Voltage (V)
Fig.10 - Source-Drain Diode Forward Voltage
May 13,2015-REV.02
PAGE . 4