CH7308B-TF datasheet, PDF - EEWORLD Datasheet

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CH7308B-TF: DescriptionConsumer Circuit, CMOS, PQFP64, LEAD FREE, LQFP-64; CategoryOther integrated circuit (IC) Consumption circuit; File Size288KB，22 Pages; ManufacturerCHRONTEL; Websitehttp://www.chrontel.com.cn/; Environmental Compliance; Quintiles Integrated Circuit (Shanghai) Co., Ltd. is a wholly-owned subsidiary of Chrontel, Inc. in Shanghai. Founded in 1986, Chrontel is a company engaged in the research and development and production of mixed-signal integrated circuits. Headquartered in San Jose, Silicon Valley, USA, Chrontel has many subsidiaries and offices around the world. Our products include TV decoders, TV encoders, DVI/LVDS/HDMI encoders, digital TV demodulators, image and audio processing, display controllers and other digital-analog hybrid chips. Our products are used by many well-known OEM manufacturers such as DELL, HP, SONY, TOSHIBA, FUJITSU, etc., and we have cooperated with well-known manufacturers such as Intel for many years.

Quintiles Integrated Circuit (Shanghai) Co., Ltd. was established in 2003 and is located in Zhangjiang Hi-Tech Development Zone, Pudong. Our business includes the research, development, design, testing, production of integrated circuits and the research, design, development, production of related software; the design, debugging and maintenance of system integration; and the provision of related technical consulting and technical maintenance. We have a team of highly qualified and educated employees and enjoy comprehensive technical support from the head office. We hope that more people of insight will join us to jointly build a successful integrated circuit company.

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CH7308B-TF Overview

Consumer Circuit, CMOS, PQFP64, LEAD FREE, LQFP-64

CH7308B-TF Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	CHRONTEL
Parts packaging code	QFP
package instruction	LEAD FREE, LQFP-64
Contacts	64
Reach Compliance Code	compliant
Commercial integrated circuit types	CONSUMER CIRCUIT
JESD-30 code	S-PQFP-G64
length	10 mm
Number of functions	1
Number of terminals	64
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

CH7308B-TF Preview

Chrontel

CH7308B

CH7308B SDVO

LVDS Transmitter

Features

•

General Description

The CH7308B is a display controller device, which accepts

digital graphics input signals, upscales, encodes, and transmits

data through an LVDS transmitter to a LCD panel. This

device accepts one channel of RGB data over three pairs of

serial data ports.

The LVDS Transmitter includes a low jitter PLL to generate a

high frequency serialized clock and all circuitry required to

upscale, encode, serialize and transmit data. The CH7308B

supports a maximum pixel rate of 165MP/s.

The LVDS transmitter includes a panel fitting up-scaler and a

programmable dither function to support 18-bit LCD panels.

Data is encoded into commonly used formats, including those

specified in the OpenLDI and SPWG specifications.

Serialized data is outputted on three to eight differential

channels.

Single/Dual LVDS Transmitter up to 165Mpixels/s

Support resolutions up to 1600x1200 (1920x1200

with reduced blanking)

LVDS low jitter PLL accepts spread spectrum input

LVDS 18-bit and 24-bit outputs

2D dither engine

Panel protection and power sequencing

High-speed SDVO

serial (1G~2Gbps) AC-coupled

differential RGB inputs

Low voltage interface support to graphics device

Programmable power management

Fully programmable through serial port

Configuration through OpCodes

Complete Windows driver support

Boundary scan support

Offered in a 64-pin LQFP package

Intel Proprietary

RESET*

SPC

SPD

SDVO_CLK(+/-)

Serial Port/

Power

Control

STALL(+/-) Generator/

Power Sequencing

XTAL

SC_PROM

SD_PROM

SC_DDC

SD_DDC

SDVO_STALL(+/-)

ENAVDD

ENABKL

XI/FIN, XO

Clock Driver

SDVO_R(+/-)

SDVO_G(+/-)

SDVO_B(+/-)

Data Latch,

Serial To

Parallel

SDVO

Character

Decoder

Up-Scaler

LVDS PLL

LVDS

Encoder

LVDS

Serializer

LVDS

Driver

LDC[3:0],LDC*[3:0]

LL1C,LL1C*

LDC[7:4],LDC*[7:4]

LL2C,LL2C*

VSWING

Dither

FIFO

Figure 1: Functional Block Diagram

201-0000-064

Rev. 3.3,

1/07/2014

CHRONTEL

Table of Contents

1.0

1.1

1.2

CH7308B

Pin Assignment ............................................................................................................................. 3

Package Diagram .......................................................................................................................................3

Pin Description ..........................................................................................................................................4

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

Functional Description................................................................................................................. 6

Input Interface............................................................................................................................................6

Automatic Panel-Fitting.............................................................................................................................8

Emission Reduction Clock.........................................................................................................................9

Dithering ....................................................................................................................................................9

Power Sequencing .....................................................................................................................................9

Panel Protection .......................................................................................................................................10

Command Interface .................................................................................................................................10

3.0

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Register Control.......................................................................................................................... 13

Electrical Specifications ............................................................................................................. 13

Absolute Maximum Ratings ....................................................................................................................13

Recommended Operating Conditions ......................................................................................................13

Electrical Characteristics .........................................................................................................................14

DC Specifications ....................................................................................................................................14

AC Specifications ....................................................................................................................................16

LVDS Output Specifications ...................................................................................................................17

LVDS Output Timing ..............................................................................................................................19

5.0

6.0

Package Dimensions ................................................................................................................... 20

Revision History.......................................................................................................................... 21

201-0000-064

Rev. 3.3,

1/07/2014

CHRONTEL

1.0 Pin Assignment

1.1

Package Diagram

CH7308B

SDVO_CLK-

RESERVED

SDVO_CLK+

SDVO_B-

SDVO_B+

SDVO_G-

SDVO_G+

SDVO_R-

SDVO_R+

BSCAN

AVDD

AGND

AVDD

AGND

TEST

ENABKL

ENAVDD

AVDD_PLL

RESET*

SPC

SPD

AGND_PLL

SD_PROM

SC_PROM

SD_DDC

SC_DDC

DGDD

XI/FIN

DVDD

SDVO_STALL-

SDVO_STALL+

LDC0*

LDC0

LVDD

LDC1*

LDC1

LGND

LDC2*

LDC2

LVDD

LL1C*

LL1C

LGND

LDC3*

LDC3

Chrontel

CH7308B

Figure 2: 64 Pin LQFP Pin Out (Top View)

201-0000-064

Rev. 3.3,

1/07/2014

VSWING

LL2C*

LDC7*

LDC6*

LDC5*

LDC4*

LL2C

LVDD

LDC7

LGND

LDC6

LVDD

LDC5

LGND

LDC4

DGND

CHRONTEL

1.2

Pin Description

CH7308B

Table 1: Pin Description

Pin #

Type

Symbol

RESET*

Description

Reset* Input (Internal pull-up)

When this pin is low, the device is held in the power-on reset

condition. When this pin is high, reset is controlled through the

serial port interface.

Address Select (Internal pull-up)

This pin determines the serial port address of the device

(0,1,1,1,0,0,AS*,0).

Serial Port Clock Input

This pin functions as the clock input of the serial port interface

and operates with from 0 to 2.5V. This pin requires an external

4kΩ - 9kΩ pull-up resistor to 2.5V

Serial Port Data Input/Output

This pin functions as the bi-directional data pin of the serial port

interface and operates with inputs from 0 to 2.5V. Outputs are

driven from 0 to 2.5V. This pin requires an external

4kΩ - 9kΩ

pull-up resistor to 2.5V.

Routed Data Output to PROM

This pin functions as the bi-directional data pin of the serial port

interface for the external 5V serial EEPROM used for ADD2 card

designs. This pin requires an external 5.6K pull-up resistor to the

desired high state voltage. Leave open if unused.

Routed Clock Output to PROM

This pin functions as the clock bus of the serial port interface for

the external 5V serial EEPROM used for ADD2 card designs.

This pin requires an external 5.6K pull-up resistor to the desired

high state voltage. Leave open if unused.

Routed Serial Port Data Output to DDC

This pin functions as the bi-directional data pin of the serial port

to the DDC of the receiver. This pin requires an external 4–9kΩ

pull-up resistor to the desired high state voltage. Leave open if

unused.

Routed Serial Port Clock Output to DDC

This pin functions as the clock bus of the serial port to the DDC of

the receiver. This pin requires an external 4–9kΩ pull-up resistor

to the desired high state voltage. Leave open if unused.

Panel Power Enable

Enable LCD panel VDD (2.5V).

Backlight Enable

Enable backlight of LCD panel (2.5V).

In/Out

SPC

In/Out

SPD

In/Out

SD_PROM

In/Out

SC_PROM

In/Out

SD_DDC

In/Out

SC_DDC

Out

ENAVDD

ENABKL

BSCAN

BSCAN (internal pull-low)

This pin should be pulled low with a 10K ohm resistor. This pin

enables the boundary scan for in-circuit testing. Voltage level is 0

to DVDD.

TEST

Internal test pin to monitor the state of the ENEXBUF (External

Buffer Enable) signal. See TB49 for details. If the ENEXBUF

signal does not need to be monitored, this pin may be left open.

Reserved

(internal pull-low)

This pin should be pulled low with a 10K ohm resistor.

Out

TEST

Reserved

201-0000-064

Rev. 3.3,

1/07/2014

CHRONTEL

Pin#

51, 52, 54,

55, 57, 58

Type

Symbol

SDVO_R+/-

SDVO_G+/-

SDVO_B+/-

CH7308B

Description

SDVO Data Channel Inputs

These pins accept 3 AC-coupled differential pair of inputs from

the digital video port of a graphics controller. These 3 pairs of

inputs can be R, G, B. The differential p-p input voltage has a

maximum value of 1.2V, with a minimum value of 175mV.

Differential Clock Input associated with SDVO Data Channel

(SDVO_R+/-, SDVO_G+/-, SDVO_B+/-)

These pins accept one AC-coupled differential pair of inputs from

the digital video port of a graphics controller. The range of this

clock pair is 100~200MHz. For specific pixel rates in specific

modes, this clock pair will run at an integer multiple of the pixel

rate. Refer to section 2.1.2 for details.

Stall Signal Pair associated with SDVO Data Channel

(SDVO_R+/-, SDVO_G+/-, SDVO_B+/-)

These pins output one AC-coupled differential pair of signals used

as a stall indication for a VGA controller, which is capable of

driving out SDVO_R+/-, SDVO_G+/-, SDVO_B+/- data. When

toggling between 100MHz and 200MHz, the stall indication state

is asserted (‘1’ value); when not toggling at all the state is de-

asserted (‘0’ value). The differential p-p output voltage has a

maximum value of 1.2V, with a minimum value of 175mV.

LVDS Differential Clock Channel 1

LVDS Differential Clock Channel 2

LVDS Differential Data[3:0]

60, 61

SDVO_CLK+/-

47, 48

Out

SDVO_STALL+/-

36, 37

17, 18

33, 39, 42,

45, 34, 40,

43, 46

20, 23, 26,

29, 21, 24,

27, 30

Out

LL1C, LL1C*

LL2C, LL2C*

LDC[3:0], LDC*[3:0]

Out

LDC[7:4], LDC*[7:4]

LVDS Differential Data [7:4]

VSWING

XI/FIN

Out

16, 49

13, 31

19, 25, 38,

22, 28, 35,

56, 62

53, 59

Power

DVDD

DGND

LVDD

LGND

AVDD

AGND

AVDD_PLL

AGND_PLL

LVDS Swing Control

This pin sets the swing level of the LVDS outputs. A 2.4KOhm

resistor should be connected between this pin and LGND using

short and wide traces.

Crystal Input/External Reference Input

A parallel resonant 14.31818 MHz crystal (+/-1000 ppm) should

be attached between this pin and XO. Alternatively, an external

CMOS compatible clock may be used to drive the XI/FIN input.

Crystal Output

A parallel resonant 14.31818 MHz crystal (+/-1000 ppm) should

be attached between this pin and XI/FIN. However, if an external

CMOS clock is attached to XI/FIN, XO should be left open.

Digital Supply Voltage (2.5V)

Digital Ground

LVDS Supply Voltage (3.3V)

LVDS Ground

Analog Supply Voltage (2.5V)

Analog Ground

LVDS PLL Supply Voltage (3.3V)

LVDS PLL Ground

201-0000-064

Rev. 3.3,

1/07/2014

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