NT512D72S4PAKG-8B datasheet, PDF

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NT512D72S4PAKG-8B: DescriptionDDR DRAM Module, 64MX72, 0.8ns, CMOS, DIMM-184; Categorystorage storage; File Size1MB，15 Pages; ManufacturerNanya; Websitehttp://www.nanya.com/cn; Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.

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NT512D72S4PAKG-8B Overview

DDR DRAM Module, 64MX72, 0.8ns, CMOS, DIMM-184

NT512D72S4PAKG-8B Parametric

Parameter Name	Attribute value
Maker	Nanya
Parts packaging code	DIMM
package instruction	DIMM, DIMM184
Contacts	184
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.8 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	125 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N184
memory density	4831838208 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	184
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL

NT512D72S4PAKG-8B Preview

NT512D72S4PAKG

512MB : 64M x 72

Registered DDR SDRAM DIMM

184pin Registered DDR SDRAM MODULE

Based on 64Mx4 DDR SDRAM

Features

• 184-Pin Registered 8-Byte Dual In-Line Memory Module

• 64Mx72 Double Data Rate (DDR) SDRAM DIMM

• Performance:

PC1600

Speed Sort

DIMM

CAS

Latency

Clock Frequency

Clock Cycle

DQ Burst Frequency

one-half clock post-amble

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

Unit

MHz

- Device

CAS

Latency: 2, 2.5

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 13/11/1 Addressing (row/column/bank)

• 7.8 µs Max. Average Periodic Refresh Interval

• Serial Presence Detect

• Gold contacts

• SDRAMs in 66-pin TSOP Type II Package

PC2100

-75B

3.5

133

7.5

266

-7K

133

7.5

266

-8B

100

200

• Intended for 100 MHz and 133 MHz applications

• Inputs and outputs are SSTL-2 compatible

• V

= 2.5Volt ± 0.2, V

DDQ

= 2.5Volt ± 0.2

• SDRAMs have 4 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• Bi-directional data strobe with one clock cycle preamble and

One clock cycle added for registered DIMMs to account for input register.

Description

NT512D72S4PAKG is a Registered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),

organized as a one-bank 64Mx72 high-speed memory array. The module uses eighteen 64Mx4 DDR SDRAMs in 400 mil TSOP II

packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs.

The use of these

common design files minimizes electrical variation between suppliers. All NANYA 184 DDR SDRAM DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25” long space-saving footprint.

The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to

266 MHz. Prior to any access operation, the device

CAS

latency and burst type/ length/operation type must be programmed into the

DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. Clock enable CKE0 controls all devices

on the DIMM.

The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of

serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

Ordering Information

Part Number

NT512D72S4PAKG-7K

Speed

143MHz (7ns @ CL = 2.5)

133MHz (7.5ns @ CL= 2)

133MHz (7.5ns @ CL= 2.5)

100MHz (10ns @ CL = 2)

125MHz (8ns @ CL = 2.5)

100MHz (10ns @ CL = 2)

DDR266A

PC2100

Organization

Leads

Power

NT512D72S4PAKG-75B

DDR266B

PC2100

64Mx72

Gold

2.5V

NT512D72S4PAKG-8B

DDR200

PC1600

REV 0.2 (Preliminary)

09/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D72S4PAKG

512MB : 64M x 72

Registered DDR SDRAM DIMM

Pin Description

CK0,

CK0

CKE0

RAS

CAS

A0-A9, A11, A12

A10/AP

BA0, BA1

RESET

REF

DDID

Differential Clock Inputs

Clock Enable

Row Address Strobe

Column Address Strobe

Write Enable

Chip Selects

Address Inputs

Address Input/Autoprecharge

SDRAM Bank Address Inputs

Reset pin

Ref. Voltage for SSTL_2 inputs

Identification flag.

DQ0-DQ63

CB0-CB7

DQS0-DQS17

DDQ

SCL

SDA

SA0-2

DDSPD

Data input/output

Check Bit Data Input/Output

Bidirectional data strobes

Power (2.5V)

Supply voltage for DQs(2.5V)

Ground

No Connect

Serial Presence Detect Clock Input

Serial Presence Detect Data input/output

Serial Presence Detect Address Inputs

Serial EEPROM positive power supply(2.5V)

Pinout

Front

REF

DQ0

DQ1

DQS0

DQ2

DQ3

RESET

DQ8

DQ9

DQS1

DDQ

DQ10

DQ11

CKE0

DDQ

DQ16

DQ17

DQS2

DQ18

DDQ

DQ19

Front

DQ24

DQ25

DQS3

DQ26

DQ27

CB0

CB1

DQS8

CB2

CB3

BA1

KEY

DQ32

DDQ

DQ33

DQS4

DQ34

BA0

DQ35

DQ40

Front

DDQ

DQ41

CAS

DQS5

DQ42

DQ43

DQ48

DQ49

DDQ

DQS6

DQ50

DQ51

DDID

DQ56

DQ57

DQS7

DQ58

DQ59

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

DQ4

DQ5

DDQ

DQS9

DQ6

DQ7

DDQ

DQ12

DQ13

DQS10

DQ14

DQ15

DDQ

DQ20

A12

DQ21

A11

DQS11

DQ22

DQ23

145

146

147

148

149

150

151

152

153

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Back

DQ28

DQ29

DDQ

DQS12

DQ30

DQ31

CB4

CB5

DDQ

CK0

DQS17

A10

CB6

DDQ

CB7

KEY

DQ36

DQ37

DQS13

DQ38

DQ39

DQ44

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

RAS

DQ45

DDQ

DQS14

DQ46

DQ47

DDQ

DQ52

DQ53

DQS15

DQ54

DQ55

DDQ

DQ60

DQ61

DQS16

DQ62

DQ63

DDQ

SA0

SA1

SA2

DDSPD

REV 0.2 (Preliminary)

09/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D72S4PAKG

512MB : 64M x 72

Registered DDR SDRAM DIMM

Input/Output Functional Description

Symbol

CK0

Type

(SSTL)

Polarity

Positive

Edge

Function

The positive line of the differential pair of system clock inputs which drives the input to

the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the

rising edge of their associated clocks.

the on-DIMM PLL.

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh

mode.

Enables the associated SDRAM command decoder when low and disables the

(SSTL)

Active

Low

Active

Low

command

decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue.

RAS

CAS

REF

DDQ

BA0, BA1

(SSTL)

Supply

(SSTL)

When sampled at the positive rising edge of the clock,

RAS

CAS

define the

operation to be executed by the SDRAM.

Reference voltage for SSTL-2 inputs

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

Selects which SDRAM bank is to be active.

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9, A11 defines the column address

(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,

A0 - A9

A10/AP

A11, A12

AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write

(SSTL)

cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be

precharged. If AP is low, autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to

pre-charge.

DQ0 - DQ63,

DQ0 – DQ63

CB0 – CB7

DD,

DQS0 – DQS17

(SSTL)

Supply

Active

High

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM

configurations.

Power and ground for the DDR SDRAM input buffers and core logic

CK0

(SSTL)

Negative The negative line of the differential pair of system clock inputs which drives the input to

Edge

Active

High

CKE0

RESET

SA0 – SA2

SDA

SCL

DDSPD

Negative

and

(SSTL)

Data strobe for input and output data

Positive

Edge

Active

(LVC-MOS)

Low

Address inputs. Connected to either V

or V

on the system board to configure the

Serial Presence Detect EEPROM address.

Supply

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V

to act as a pullup.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V

to act as a pullup.

Serial EEPROM positive power supply.

REV 0.2 (Preliminary)

09/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D72S4PAKG

512MB : 64M x 72

Registered DDR SDRAM DIMM

Functional Block Diagram

(1 Bank, 64Mx4 DDR SDRAMs)

RS0

DQS0

DQ0

DQ1

DQ2

DQ3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

DQ8

DQ9

DQ10

DQ11

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

DQS

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

DQS

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CB0

CB1

CB2

CB3

I/O 0

I/O 1

I/O 2

I/O 3

DQ4

DQ5

DQ6

DQ7

DM0/DQS9

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

DQS

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

DQS

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

DQS1

DM1/DQS10

D10

DQS2

DQ16

DQ17

DQ18

DQ19

DM2/DQS11

D11

DQ20

DQ21

DQ22

DQ23

DQS3

DQ24

DQ25

DQ26

DQ27

DM3/DQS12

D12

DQ28

DQ29

DQ30

DQ31

DQS4

DM4/DQS13

D13

DQS5

DM5/DQS14

D14

DQS6

DM6/DQS15

D15

DQS7

DQ56

DQ57

DQ58

DQ59

DM7/DQS16

D16

DQ60

DQ61

DQ62

DQ63

DQS8

DM8/DQS17

D17

BA0-BA1

A0-A12

RAS

CAS

CKE0

PCK

Notes :

RS0

RBA0-RBA1

RA0-RA12

RRAS

RCAS

RCKE0

RWE

RESET

: SDRAMs D0-D17

BA0-BA1 : SDRAMs D0-D17

A0-A12 : SDRAMs D0-D17

RAS

: SDRAMs D0-D17

CAS

: SDRAMs D0-D17

CKE : SDRAMs D0-D17

: SDRAMs D0-D17

DDSPD

DDQ

REF

DDID

Serial PD

D0-D17

Strap : see Note 4

Serial PD

SCL

WP A0

SA0

SA1

SA2

SDA

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/CS relationships are maintained as shown.

3. DQ/DQS resistors are 22 Ohms.

4. V

DDID

strap connections (for memory device V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

5. Address and control resistors are 22 Ohms.

CK0,

CK0

--------- PLL*

* Wire per Clock Loading Table/Wiring Diagrams

REV 0.2 (Preliminary)

09/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D72S4PAKG

512MB : 64M x 72

Registered DDR SDRAM DIMM

Serial Presence Detect --

Part 1 of 2

64Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 64Mx4, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value

Byte

Description

Number of Serial PD Bytes Written during

Production

Total Number of Bytes in Serial PD device

Fundamental Memory Type

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Bank

Data Width of Assembly

Data Width of Assembly (cont’)

Voltage Interface Level of this Assembly

DDR SDRAM Device Cycle Time at CL=2.5

DDR SDRAM Device Access Time from

Clock at CL=2.5

DIMM Configuration Type

Refresh Rate/Type

Primary DDR SDRAM Width

Error Checking DDR SDRAM Device Width

DDR SDRAM Device Attr: Min CLk Delay,

Random Col Access

DDR SDRAM Device Attributes:

Burst Length Supported

DDR SDRAM Device Attributes: Number of

Device Banks

DDR SDRAM Device Attributes: CAS

Latencies Supported

DDR SDRAM Device Attributes: CS Latency

DDR SDRAM Device Attributes: WE Latency

DDR SDRAM Device Attributes:

DDR SDRAM Device Attributes: General

Minimum Clock Cycle at CL=2

Maximum Data Access Time from Clock at

CL=2

Minimum Clock Cycle Time at CL=1

Maximum Data Access Time from Clock at

CL=1

Minimum Row Precharge Time (t

)

Minimum Row Active to Row Active delay

RRD

)

Minimum RAS to CAS delay (t

RCD

)

Minimum RAS Pulse Width (t

RAS

)

Module Bank Density

Address and Command Setup Time Before

Clock

Address and Command Hold Time After

Clock

Data Input Setup Time Before Clock

Data Input Hold Time After Clock

Reserved

SPD Revision

Checksum Data

Initial

0.9ns

0.5ns

20ns

15ns

20ns

45ns

2/2.5

7ns

0.75ns

DDR266A DDR266B

-7K

36-61

-75B

128

256

SDRAM DDR

X72

SSTL 2.5V

7.5ns

0.75ns

ECC

7.8us / SR

1 Clock

2, 4, 8

2/2.5

Differential Clock, PLL, REGISTER

+/-0.2V Voltage Tolerance

7.5ns

0.75ns

10ns

0.75ns

N/A

20ns

15ns

20ns

45ns

512MB

0.9ns

0.5ns

Undefined

Initial

1.1ns

0.6ns

20ns

15ns

20ns

50ns

10ns

0.8ns

2/2.5

8ns

0.8ns

DDR200

-8B

Serial PD Data Entry (Hexadecimal) Note

DDR266A DDR266B

-7K

-75B

DDR200

-8B

REV 0.2 (Preliminary)

09/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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