DDR3
ECC ADDRESS PARITY LP DIMM
VR7EAxx7254xBx
Module Configuration
VMS Part Number
VR7EA567254FBZ
VR7EA567254FBA
VR7EA567254FBB
VR7EA567254FBC
VR7EA567254FBD
VR7EA567254FBE
VR7EA127254GBZ
VR7EA127254GBA
VR7EA127254GBB
VR7EA127254GBC
VR7EA127254GBD
VR7EA127254GBE
VR7EA127254FBZ
VR7EA127254FBA
VR7EA127254FBB
VR7EA127254FBC
VR7EA127254FBD
VR7EA127254FBE
VR7EA1G7254GBZ
VR7EA1G7254GBA
VR7EA1G7254GBB
VR7EA1G7254GBC
VR7EA1G7254GBD
VR7EA1G7254GBE
VR7EA2G7254GEZ
VR7EA2G7254GEA
VR7EA2G7254GEB
VR7EA2G7254GEC
VR7EA2G7254GED
VR7EA2G7254GEE
Capacity
2GB
2GB
2GB
2GB
2GB
2GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
8GB
8GB
8GB
8GB
8GB
8GB
16GB
16GB
16GB
16GB
16GB
16GB
Module
Configuration
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
1Gx72
1Gx72
1Gx72
1Gx72
1Gx72
1Gx72
2Gx72
2Gx72
2Gx72
2Gx72
2Gx72
2Gx72
Device
Configuration
256Mx4 (18)
256Mx4 (18)
256Mx4 (18)
256Mx4 (18)
256Mx4 (18)
256Mx4 (18)
512Mx4 (18)
512Mx4 (18)
512Mx4 (18)
512Mx4 (18)
512Mx4 (18)
512Mx4 (18)
256Mx4 (36)
256Mx4 (36)
256Mx4 (36)
256Mx4 (36)
256Mx4 (36)
256Mx4 (36)
512Mx4 (36)
512Mx4 (36)
512Mx4 (36)
512Mx4 (36)
512Mx4 (36)
512Mx4 (36)
512Mx4x2 (36)
512Mx4x2 (36)
512Mx4x2 (36)
512Mx4x2 (36)
512Mx4x2 (36)
512Mx4x2 (36)
Device Package
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
DDP TFBGA
DDP TFBGA
DDP TFBGA
DDP TFBGA
DDP TFBGA
DDP TFBGA
Module
Ranks
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
Performance
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
CAS Latency
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
Features
•
•
•
•
•
•
•
•
JEDEC standard 1.5V ± 0.075V Power Supply
o
VDD = 1.5V ±0.075V
o
VDDSPD = +3.0V to +3.6V
240-pin Registered Dual-In-Line Memory Module with
parity bit for address and control bus.
8 Internal Banks.
Programmable CAS Latency: 6, 7, 8, 9, 10
Programmable CAS Write Latency (CWL).
Programmable Additive Latency (Posted CAS).
Fixed burst chop (BC) of 4 and burst length (BL) of 8 via
the mode register set (MRS)
Selectable BC4 or BL8 on-the-fly (OTF)
•
•
•
•
•
•
•
•
•
•
On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
Refresh. Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write Leveling
and Multi Purpose Register (MPR) Read Pattern.
Serial Presence Detect with EEPROM.
On-DIMM Thermal Sensor.
Asynchronous Reset.
LP RDIMM dimensions: 133.35 mm x 30 mm.
2/4 rank modules include heat spreader.
RoHS Compliant* (see last page)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website:
http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5EAxx7254xBx Revision B1 Created By: Brian Ouellette
Page 1 of 30
DDR3
ECC ADDRESS PARITY LP DIMM
VR7EAxx7254xBx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0
/CK0
CKE[1:0]
TYPE
IN
IN
IN
POLARITY
Positive Edge
Negative Edge
Active High
DESCRIPTION
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM
Clock
Driver.
Negative line of the differential pair of system clock inputs that drives the input to the on-
DIMM Clock Driver.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations
continue. These input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When both S[1:0] are high, all register
outputs (except CKE, ODT and Chip select) remain in the previous state. For modules
supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs.
On-Die Termination control signals
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operation to be executed by the SDRAM.
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1,
Par_In, ODT0 and ODT1.
Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also
determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the
memory array in the respective bank. A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also
utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address
inputs also provide the op-code during Mode Register Set commands.
Data and Check Bit Input/Output pins
Power and ground for the DDR SDRAM input buffers and core logic.
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
TDQS, TDQS# is applicable for X8 DRAMs only. When enabled via Mode Register A11=1
in MR1, DRAM will enable the same termination resistance function on TDQS, TDQS#
that is applied to DQS, DQS#. When disabled via mode register A11=0 in MR1, DM,
TDQS will provide the data mask function and TDQS# is not used. X4/X16 DRAMs must
disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a
pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
S[3:0]#
IN
Active Low
ODT[1:0]
RAS#, CAS#,
WE#
VREFDQ
VREFCA
BA[2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A[15:13,
12/BC,11,
10/AP,9:0]
DQ [63:0],
CB [7:0]
VDD, VSS
DM [8:0]
VDD, VSS
VTT
DQS[17:0]
DQS [17:0]#
TDQS[17:9],
TDQS[17:9]#
SA [2:0]
SDA
SCL
IN
-
I/O
Supply
IN
Supply
Supply
I/O
I/O
OUT
-
-
Active High
Positive Edge
Negative Edge
IN
I/O
IN
-
-
-
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website:
http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5EAxx7254xBx Revision B1 Created By: Brian Ouellette
Page 4 of 30
DDR3
ECC ADDRESS PARITY LP DIMM
VR7EAxx7254xBx
PIN FUNCTION DESCRIPTION
SYMBOL
EVENT#
VDDSPD
RESET#
Par_In
Err_Out#
TEST
TYPE
OUT
(open drain)
Supply
IN
IN
OUT
POLARITY
Active Low
-
DESCRIPTION
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL.
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and
register(s) will be set to low level (the PLL will remain synchronized with the input clock)
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website:
http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5EAxx7254xBx Revision B1 Created By: Brian Ouellette
Page 5 of 30
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