IS24C128B
TABLE OF COnTEnTS
Features ……………………………………………………….……………............3
Description ………………………………………………...………………............3
Functional Block Diagram ………………………………………………............4
Pin Configuration & Description ……………………………………….............5
Device Operations …..……………………………………………………............6
Absolute Maximum Ratings …………………………………………….............12
DC Characteristics ………………………………………………………..............12
AC Characteristics ………………………………………………………..............13
Ordering Information ……………………………………………………..............15
Packaging Information ….………………………………………………..............16
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00F
09/18/09
IS24C128B
128K-bit
2-WIRE SERIAL CMOS EEPROM
FEATURES
• Two-Wire Serial Interface, I
2
C
TM
compatible
– Bi-directional data transfer protocol
• Wide Voltage Operation
– Vcc = 1.8V to 5.5V
• 400 KHz (1.8V) and 1 MHz (5.0V) compatibility
• 128K-bit memory
• Low Power CMOS Technology
– Active Current less than 3 mA (1.8V)
– Standby Current less than 15 µA (1.8V)
• Hardware Data Protection
– Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
– 5 ms @ 1.8V
• Memory Organization:
–16Kx8 (256 pages of 64 bytes)
• 64-Byte Page Write Buffer
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 40 Years
• Industrial temperature range
• Packages: SOIC/SOP (JEDEC) and TSSOP
PRELIMInARY InFORMATIOn
OCTOBER 2009
DESCRIPTIOn
The IS24C128B is an electrically erasable PROM
device that uses the standard 2-wire interface for
communications. The IS24C128B is 128K-bit (16Kx8).
These EEPROM are offered in a wide operating voltage
range of 1.8V to 5.5V to be compatible with most
application voltages. ISSI designed the IS24C128B to
be an efficient 2-wire EEPROM solution. The devices
are offered in lead free, RoHS, halogen free or Green.
The available package types are 8-pin SOIC (JEDEC)
and TSSOP.
The IS24C128B maintains compatibility with the
popular 2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master device
such as a microcontroller is usually connected to one
or more Slave devices such as the IS24C128B. The
bit stream over the SDA line includes a series of bytes,
which identifies a particular Slave device, an instruction,
an address within that Slave device, and a series of
data, if appropriate. The IS24C128B has a Write Protect
pin (WP) to allow blocking of any write instruction
transmitted over the bus.
Copyright © 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equip-
ment, aerospace systems, or for other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best
performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services described
herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
Intregrated Silicon Solution, Inc. - www.issi.com
Rev. 00F
09/18/09
3
IS24C128B
PIN CONFIGURATION
8-Pin SOIC, TSSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
PIn DESCRIPTIOnS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
with the IS24C32A/64A. When pins are hardwired, as many
as eight 128K devices may be addressed on a single bus
system. When the pins are not hardwired, the default values
of A0, A1, and A2 are zero.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an
open drain output and can be wire Or'ed with other open
drain or open collector outputs. The SDA bus a pullup
resistor to Vcc.
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc
the entire array becomes Write Protected (Read only).
When WP is tied to GND or left floating, normal read/write
operations are allowed to the device.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00F
09/18/09
5
FPGA/CPLD
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