NT5SV32M8BS-6K datasheet, PDF - EEWORLD Datasheet

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NT5SV32M8BS-6K: DescriptionSynchronous DRAM, 32MX8, 5ns, CMOS, PDSO54, 0.400 INCH, LEAD AND HALOGEN FREE, PLASTIC, TSOP2-54; Categorystorage storage; File Size3MB，65 Pages; ManufacturerNanya; Websitehttp://www.nanya.com/cn; Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.

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NT5SV32M8BS-6K Overview

Synchronous DRAM, 32MX8, 5ns, CMOS, PDSO54, 0.400 INCH, LEAD AND HALOGEN FREE, PLASTIC, TSOP2-54

NT5SV32M8BS-6K Parametric

Parameter Name	Attribute value
Maker	Nanya
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	167 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
length	22.22 mm
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	54
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8
Maximum standby current	0.002 A
Maximum slew rate	0.21 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

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NT5SV64M4BS / NT5SV64M4BT

NT5SV32M8BS / NT5SV32M8BT

NT5SV16M16BS / NT5SV16M16BT

256Mb Synchronous DRAM

Features

•

High Performance:

6K/6KI

CL=3

Clock Frequency

Clock Cycle

Clock Access

Time

75B/75BI

CL=3

133

7.5

—

5.4

Units

MHz

166

—

Clock Access Time

1. Terminated load. See AC Characteristics on page 37

2. Unterminated load. See AC Characteristics on page 37

3. t

= t

RCD

= 2 CKs

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• Four Banks controlled by BA0/BA1 (Bank Select)

•

Programmable CAS Latency: 2, 3

Programmable Burst Length: 1, 2, 4, 8 or full page

Programmable Wrap: Sequential or Interleave

Multiple Burst Read with Single Write Option

Automatic and Controlled Precharge Command

Data Mask for Read/Write control (x4, x8)

Dual Data Mask for byte control (x16)

Auto Refresh (CBR) and Self Refresh

Suspend Mode and Power Down Mode

Standard Power operation

8192 refresh cycles/64ms

Random Column Address every CK (1-N Rule)

Single 3.3V

0.3V Power Supply

LVTTL compatible

Package: 54-pin 400 mil TSOP-Type II

Lead-free & Halogen-free product available

Description

The NT5SV64M4BS, NT5SV64M4BT, NT5SV32M8BS,

NT5SV32M8BT, NT5SV16M16BS, and NT5SV16M16BT are

four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O

x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4

Bank, respectively. These synchronous devices achieve

high-speed data transfer rates of up to 166MHz by employing

a pipeline chip architecture that synchronizes the output data

to a system clock.

The device is designed to comply with all JEDEC standards

set for synchronous DRAM products, both electrically and

mechanically. All of the control, address, and data input/out-

put (I/O or DQ) circuits are synchronized with the positive

edge of an externally supplied clock.

RAS, CAS, WE, and CS are pulsed signals which are exam-

ined at the positive edge of each externally applied clock

(CK). Internal chip operating modes are defined by combina-

tions of these signals and a command decoder initiates the

necessary timings for each operation. A fifteen bit address

bus accepts address data in the conventional RAS/CAS mul-

tiplexing style. Thirteen row addresses (A0-A12) and two

bank select addresses (BA0, BA1) are strobed with RAS.

Eleven column addresses (A0-A9, A11) plus bank select

addresses and A10 are strobed with CAS. Column address

A11 is dropped on the x8 device, and column addresses A11

and A9 are dropped on the x16 device.

Prior to any access operation, the CAS latency, burst length,

and burst sequence must be programmed into the device by

address inputs A0-A12, BA0, BA1 during a mode register set

cycle. In addition, it is possible to program a multiple burst

sequence with single write cycle for write through cache

operation.

Operating the four memory banks in an interleave fashion

allows random access operation to occur at a higher rate

than is possible with standard DRAMs. A sequential and gap-

less data rate of up to 166MHz is possible depending on

burst length, CAS latency, and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are sup-

ported.

REV 1.7

Oct 2008

NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

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