VR7EU286458FBC datasheet, PDF - EEWORLD Datasheet

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VR7EU286458FBC: DescriptionDDR DRAM Module, 128MX72, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size275KB，24 Pages; ManufacturerViking; Websitehttp://www.viking.com.tw/; Environmental Compliance; Guangjie Technology was established in October 1997 in Hsinchu Science Park. It is the first professional manufacturer in Taiwan that combines thin film/thick film process technology with high-frequency passive component/module design and development capabilities. It has an excellent technical R&D team and is committed to the research and development of thin film process technology and the design and development of high-frequency component/module integration. It provides key components such as integrated passive components and high-frequency modules that meet the high-frequency and miniaturization needs of system products. It has successfully integrated passive components such as resistors/capacitors/inductors/diodes (Integrated Passive Devices, IPDs), which can be widely used in mobile personal electronic products. Anti-static and electromagnetic filtering (ESD & EMI Filter), etc.

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VR7EU286458FBC Overview

DDR DRAM Module, 128MX72, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240

VR7EU286458FBC Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Viking
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	240
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.255 ns
Other features	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX
JESD-30 code	R-XDMA-N240
length	133.35 mm
memory density	8589934592 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	240
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	128MX64
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum seat height	29.972 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.81 mm

VR7EU286458FBC Preview

DDR3

UNBUFFERED DIMM

VR7EUxxxx58xxx

Module Configuration Non-ECC

Viking Part Number

VR7EU286458FBZ

VR7EU286458FBA

VR7EU286458FBB

VR7EU286458FBC

VR7EU286458FBD

VR7EU286458FBE

VR7EU566458GBZ

VR7EU566458GBA

VR7EU566458GBB

VR7EU566458GBC

VR7EU566458GBD

VR7EU566458GBE

VR7EU566458FBZ

VR7EU566458FBA

VR7EU566458FBB

VR7EU566458FBC

VR7EU566458FBD

VR7EU566458FBE

VR7EU126458GBZ

VR7EU126458GBA

VR7EU126458GBB

VR7EU126458GBC

VR7EU126458GBD

VR7EU126458GBE

Capacity

1GB

2GB

4GB

Module

Configuration

128Mx64

256Mx64

512Mx64

Device

Configuration

128Mx8 (8)

256Mx8 (8)

128Mx8 (16)

256Mx8 (16)

Device Package

TFBGA

Module

Ranks

Performance

PC3-6400

PC3-8500

PC3-10600

PC3-6400

PC3-8500

PC3-10600

PC3-6400

PC3-8500

PC3-10600

PC3-6400

PC3-8500

PC3-10600

CAS Latency

CL6 (6-6-6)

CL7 (7-7-7)

CL8 (8-8-8)

CL9 (9-9-9)

CL10 (10-10-10)

CL6 (6-6-6)

CL7 (7-7-7)

CL8 (8-8-8)

CL9 (9-9-9)

CL10 (10-10-10)

CL6 (6-6-6)

CL7 (7-7-7)

CL8 (8-8-8)

CL9 (9-9-9)

CL10 (10-10-10)

CL6 (6-6-6)

CL7 (7-7-7)

CL8 (8-8-8)

CL9 (9-9-9)

CL10 (10-10-10)

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS7EUxxxx58xxx Revision A4 Created By: Brian Ouellette

Page 1 of 24

DDR3

UNBUFFERED DIMM

VR7EUxxxx58xxx

Module Configuration ECC

Viking Part Number

VR7EU287258FBZ

VR7EU287258FBA

VR7EU287258FBB

VR7EU287258FBC

VR7EU287258FBD

VR7EU287258FBE

VR7EU567258GBZ

VR7EU567258GBA

VR7EU567258GBB

VR7EU567258GBC

VR7EU567258GBD

VR7EU567258GBE

VR7EU567258FBZ

VR7EU567258FBA

VR7EU567258FBB

VR7EU567258FBC

VR7EU567258FBD

VR7EU567258FBE

VR7EU127258GBZ

VR7EU127258GBA

VR7EU127258GBB

VR7EU127258GBC

VR7EU127258GBD

VR7EU127258GBE

Capacity

1GB

2GB

4GB

Module

Configuration

128Mx72

256Mx72

512Mx72

Device

Configuration

128Mx8 (9)

256Mx8 (9)

128Mx8 (18)

256Mx8 (18)

Device Package

TFBGA

Module

Ranks

Performance

PC3-6400

PC3-8500

PC3-10600

PC3-6400

PC3-8500

PC3-10600

PC3-6400

PC3-8500

PC3-10600

PC3-6400

PC3-8500

PC3-10600

CAS Latency

CL6 (6-6-6)

CL7 (7-7-7)

CL8 (8-8-8)

CL9 (9-9-9)

CL10 (10-10-10)

CL6 (6-6-6)

CL7 (7-7-7)

CL8 (8-8-8)

CL9 (9-9-9)

CL10 (10-10-10)

CL6 (6-6-6)

CL7 (7-7-7)

CL8 (8-8-8)

CL9 (9-9-9)

CL10 (10-10-10)

CL6 (6-6-6)

CL7 (7-7-7)

CL8 (8-8-8)

CL9 (9-9-9)

CL10 (10-10-10)

Features

•

JEDEC standard 1.5V ± 0.075V Power Supply

VDD = 1.5V ±0.075V

VDDSPD = +3.0V to +3.6V

240-pin Dual-In-Line Memory Module.

8 Internal Banks.

Programmable CAS Latency: 6, 7, 8, 9, 10

Programmable CAS Write Latency (CWL).

Programmable Additive Latency (Posted CAS).

•

Fixed burst chop (BC) of 4 and burst length (BL) of 8 via

the mode register set (MRS)

Selectable BC4 or BL8 on-the-fly (OTF)

On-Die-Termination (ODT) and Dynamic ODT for improved

signal integrity.

Refresh. Self Refresh and Power Down Modes.

Serial Presence Detect with EEPROM.

On-DIMM Thermal Sensor.

RoHS Compliant* (see last page)

Nomenclature

Module Standard

PC3-6400

PC3 -8500

PC3-10600

PC3-12800

SDRAM Standard

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Clock

400MHz

533MHz

667MHz

800MHz

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS7EUxxxx58xxx Revision A4 Created By: Brian Ouellette

Page 2 of 24

DDR3

UNBUFFERED DIMM

VR7EUxxxx58xxx

PIN CONFIGURATIONS

Front

Side

VREFDQ 121

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

122

123

124

Back

Side

VSS

DQ4

DQ5

Front

Side

DQ25

VSS

DQS3#

DQS3

VSS

DQ26

DQ27

VSS

†CB0

†CB1

VSS

DQS8#

DQS8

VSS

†CB2

†CB3

VSS

VTT

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

KEY

169

170

171

172

173

174

175

176

177

178

179

180

Back

Side

VSS

DM3,

DQS12,

TDQS12

DQS12#,

TDQS12#

VSS

DQ30

DQ31

VSS

†CB4

†CB5

VSS

†DM8,

DQS17,

TDQS17

DQS17#,

TDQS17#

VSS

†CB6

†CB7

VSS

NC(TEST)

RESET#

Front

Side

VDD

*CK1

*CK1#

VDD

VREFCA

VDD

A10 / AP

BA0

VDD

WE#

CAS#

VDD

*S1#

*ODT1

VDD

VSS

DQ32

DQ33

VSS

DQS4#

DQS4

VSS

DQ34

DQ35

VSS

DQ40

181

182

183

184

185

186

Back

Side

VDD

CK0

CK0#

VDD

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

Front

Side

DQ41

VSS

DQS5#

DQS5

VSS

DQ42

DQ43

VSS

DQ48

DQ49

VSS

DQS6#

DQS6

VSS

DQ50

DQ51

VSS

DQ56

DQ57

VSS

DQS7#

DQS7

VSS

DQ58

DQ59

VSS

SA0

SCL

SA2

VTT

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

Side

VSS

DM5,

DQS14,

TDQS14

DQS14#,

TDQS14#

VSS

DQ46

DQ47

VSS

DQ52

DQ53

VSS

DM6,

DQS15,

TDQS15

DQS15#,

TDQS15#

VSS

DQ54

DQ55

VSS

DQ60

DQ61

VSS

DM7,

DQS16,

TDQS16

DQS16#,

TDQS16#

VSS

DQ62

DQ63

VSS

VDDSPD

SA1

SDA

VSS

VTT

VSS

DM0, DQS9,

125

TDQS9

126 DQS9#, TDQS9#

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

VSS

DQ6

DQ7

VSS

DQ12

DQ13

VSS

DM1, DQS10,

TDQS10

DQS10#,

TDQS10#

VSS

DQ14

DQ15

VSS

DQ20

DQ21

VSS

DM2, DQS11,

TDQS11

DQS11#,

TDQS11#

VSS

DQ22

DQ23

VSS

DQ28

DQ29

187 EVENT#

188

189

VDD

190

BA1

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

VDD

RAS#

S0#

VDD

ODT0

A13

VDD

VSS

DQ36

DQ37

VSS

DM4,

DQS13,

TDQS13

DQS13#,

TDQS13#

VSS

DQ38

DQ39

VSS

DQ44

DQ45

VTT

CKE0

VDD

BA2

VDD

A11

VDD

*CKE1

VDD

A15

A14

VDD

A12 / BC#

VDD

*Used on dual rank modules

† Used on ECC modules, NC on x64 configurations

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS7EUxxxx58xxx Revision A4 Created By: Brian Ouellette

Page 3 of 24

DDR3

UNBUFFERED DIMM

VR7EUxxxx58xxx

PIN FUNCTION DESCRIPTION

SYMBOL

CK0, CK1

#CK0, #CK1

CKE[1:0]

TYPE

POLARITY

Positive Edge

Negative Edge

Active High

DESCRIPTION

Positive line of the differential pair of system clock inputs.

Negative line of the differential pair of system clock inputs.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input

buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER

DOWN (row ACTIVE in any bank)

Enables the associated SDRAM command decoder when low and disables decoder when

high. When decoder is disabled, new commands are ignored and previous operations

continue. These input signals also disable all outputs (except CKE and ODT) of the

outputs (except CKE, ODT and Chip select) remain in the previous state. For modules

supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs.

On-Die Termination control signals

When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the

operation to be executed by the SDRAM.

Reference voltage for DQ0-DQ63 and CB0-CB7.

Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1,

Par_In, ODT0 and ODT1.

Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an

Active, Read, Write or Precharge command is being applied. Bank address also

determines mode register is to be accessed during an MRS cycle.

Provided the row address for Active commands and the column address

and Auto Precharge bit for Read/Write commands to select one location out of the

memory array in the respective bank. A10 is sampled during a Precharge command to

determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also

utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address

inputs also provide the op-code during Mode Register Set commands.

Data and Check Bit Input/Output pins

Power and ground for the DDR SDRAM input buffers and core logic.

Masks write data when high, issued concurrently with input data.

Power and ground for the DDR SDRAM input buffers and core logic.

Termination Voltage for Address/Command/Control/Clock nets.

Positive line of the differential data strobe for input and output data.

Negative line of the differential data strobe for input and output data.

TDQS, TDQS# is applicable for X8 DRAMs only. When enabled via Mode Register A11=1

in MR1, DRAM will enable the same termination resistance function on TDQS, TDQS#

that is applied to DQS, DQS#. When disabled via mode register A11=0 in MR1, DM,

TDQS will provide the data mask function and TDQS# is not used. X4/X16 DRAMs must

disable the TDQS function via mode register A11=0 in MR1

These signals are tied at the system planar to either VSS or VDDSPD to configure the

serial SPD EEPROM address range.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V

DDSPD

on the system planar to act as a

pullup.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.

S[3:0]#

Active Low

ODT[1:0]

RAS#, CAS#,

WE#

VREFDQ

VREFCA

BA[2:0]

Supply

Active High

Active Low

A[15:13,

12/BC,11,

10/AP,9:0]

DQ [63:0],

CB [7:0]

VDD, VSS

DM [8:0]

VDD, VSS

VTT

DQS[17:0]

DQS [17:0]#

TDQS[17:9],

TDQS[17:9]#

SA [2:0]

SDA

SCL

I/O

Supply

I/O

OUT

Active High

Positive Edge

Negative Edge

I/O

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS7EUxxxx58xxx Revision A4 Created By: Brian Ouellette

Page 4 of 24

DDR3

UNBUFFERED DIMM

VR7EUxxxx58xxx

PIN FUNCTION DESCRIPTION

SYMBOL

EVENT#

VDDSPD

RESET#

TEST

TYPE

OUT

(open drain)

Supply

POLARITY

Active Low

DESCRIPTION

This signal indicates that a thermal event has been detected in the thermal sensing

device.The system should guarantee the electrical level requirement is met for the

EVENT pin on TS/SPD part.

Serial EEPROM positive power supply wired to a separate power pin at the connector

which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.

The RESET# pin is connected to the RESET# pin on each DRAM. When low, all DRAMs

are set to a known state.

Used by memory bus analysis tools (unused (NC) on memory DIMMs)

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS7EUxxxx58xxx Revision A4 Created By: Brian Ouellette

Page 5 of 24

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