EliteMT
DRAM
FEATURES
X16 organization
FAST PAGE access mode
2
CAS
Byte/Word Read/Write operation
Single 5V (
±
10%) power supply
TTL-compatible inputs and outputs
256-cycle refresh in 4ms
Refresh modes :
RAS
only,
CAS
BEFORE
RAS
(CBR)
and HIDDEN
JEDEC standard pinout
Key AC Parameter
t
RAC
-25
-30
-35
-40
25
30
35
40
t
CAC
8
9
10
11
t
RC
43
55
65
75
t
PC
15
20
23
25
M10B11664A
64 K x 16 DRAM
FAST PAGE MODE
ORDERING INFORMATION - PACKAGE
40-pin 400mil SOJ
44 / 40-pin 400mil TSOP (TypeII)
PRODUCT NO.
M10B11664A-25J
M10B11664A-30J
M10B11664A-35J
M10B11664A-40J
M10B11664A-25T
M10B11664A-30T
M10B11664A-35T
M10B11664A-40T
TSOPII
PACKING TYPE
SOJ
GENERAL DESCRIPTION
The M10B11664A is a randomly accessed solid state memory, organized as 65,536 x 16 bits device. It offers Fast Page
mode , 5V(
±
10%) single power supply. Access time (-25,-30,-35,-40) and package type (SOJ, TSOP II) are optional features
of this family. All these family have
CAS
- before -
RAS
,
RAS
-only refresh and Hidden refresh capabilities.
Two access modes are supported by this device : Byte access and Word access. Use only one of the two
CAS
and leave
the other staying high will result in a BYTE access. WORD access happens when two
CAS
(
CASL
,
CASH
) are used.
CASL
transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and
CASH
transiting low will output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
V
CC
I/O0
I/O1
I/O2
I/O3
V
C C
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RA S
NC
A0
A1
A2
A3
V
C C
TSOP (TypeII) Top View
V
S S
I/O1 5
I/O1 4
I/O1 3
I/O1 2
V
S S
I/O1 1
I/O1 0
I/O9
I/O8
NC
CASL
CASH
OE
NC
A7
A6
A5
A4
V
S S
V
CC
I/O0
I/O1
I/O2
I/O3
V
C C
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RA S
NC
A0
A1
A2
A3
V
C C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
S S
I/O1 5
I/O1 4
I/O1 3
I/O1 2
V
S S
I/O1 1
I/O1 0
I/O 9
I/O 8
NC
CASL
CASH
OE
NC
A7
A6
A5
A4
V
S S
Elite Memory Technology Inc
Publication Date
:
Nov. 2004
Revision
:
1.3
1/15
EliteMT
FUNCTIONAL BLOCK DIAGRAM
WE
RAS
CASL
CASH
CONTROL
LOGIC
DATA-IN BUFFER
M10B11664A
16
IO0
:
IO15
CLOCK
GENERATOR
COLUMN
DECODER
256
16
DATA-OUT
BUFFER
OE
16
8
8
A0
A1
A2
A3
A4
A5
A6
A7
8
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLER
SENSE AMPLIFIERS
I/O GATING
8
256 x 16
REFRESH
COUNTER
9
8
ROW.
ADDRESS
BUFFERS(8)
8
ROW
DECODER
256 x 256 x 16
MEMORY
ARRAY
256
V
BB
GENERATOR
V
CC
V
SS
PIN DESCRIPTIONS
PIN NO.
16~19,22~25
14
28
29
13
PIN NAME
A0~A7
RAS
CASH
CASL
TYPE
Input
Input
Input
Input
DESCRIPTION
Address Input
Row Address : A0~A7
Column Address : A0~A7
Row Address Strobe
Column Address Strobe / Upper Byte Control
Column Address Strobe / Lower Byte Control
WE
OE
Input
Input
Input / Output
Supply
Ground
-
Write Enable
Output Enable
Data Input / Output
Power, 5V
Ground
No Connect
27
2~5,7~10,31~34,36~39
1,6,20
21,35,40
11,12,15,30
I/O0 ~ I/O15
V
CC
V
SS
NC
Elite Memory Technology Inc
Publication Date
:
Nov. 2004
Revision
:
1.3
2/15
EliteMT
ABSOLUTE MAXIMUM RATINGS
Voltage on Any pin Relative to Vss … ……-1V to +7V
Operating Temperature, T
A
(ambient) ….0
°
C to +70
°
C
Storage Temperature (plastic) ……….-55
°
C to +150
°
C
Power Dissipation …………………………………1.0W
Short Circuit Output Current ……………………50mA
M10B11664A
Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded. This is a stress rating
only, and functional operation of the device above those
conditions indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0
°
C
≤
T
A
≤
70
°
C ; V
CC
= 5V
±
10% unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS NOTES
Supply Voltage
Supply Voltage
Input High (Logic)Voltage
Input Low (Logic)Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Note : 1.All Voltages referenced to V
SS
0V
≤
V
I
H
≤
7V
0V
≤
V
OUT
≤
7V
Output(s) disable
I
OH
= -5 mA
I
OL
= 4.2 mA
V
CC
V
SS
V
IH
V
IL
I
LI
I
LO
V
OH
V
OL
4.5
0
2.4
-1.0
-10
-10
2.4
-
5.5
0
V
CC
+1
0.8
10
10
-
0.4
V
V
V
V
µ
A
µ
A
1
1
1
V
V
DESCRIPTION
CONDITIONS
RAS
,
CAS
cycling , t
RC
=min
SYMBOL
MAX
-25 -30 -35 -40
UNITS NOTES
Operating Current
I
CC1
170 150 130 120
4
2
4
2
4
2
4
2
mA
mA
mA
mA
mA
mA
mA
1,2
Standby Current
TTL interface,
RAS
,
CAS
= V
IH
,
D
OUT
=High-Z
CMOS interface,
RAS
,
CAS
>V
CC
-0.2V
I
CC2
RAS
only refresh Current
t
RC
= min
t
PC
= min
RAS
=V
IH
,
CAS
= V
IL
I
CC3
I
CC4
I
CC5
I
CC6
170 150 130 120
170 150 130 120
5
5
5
5
2
1,3
1
FAST Page Mode Current
Standby Current
CAS
Before
RAS
Refresh
Current
t
RC
= min
170 150 130 120
Note
:
1. ICC max is specified at the output open condition.
2. Address can be changed twice or less while
RAS
=V
IL
.
3. Address can be changed once or less while
CAS
=V
IH
.
Elite Memory Technology Inc
Publication Date
:
Nov. 2004
Revision
:
1.3
3/15
EliteMT
CAPACITANCE
(Ta = 25
°
C , V
CC
= 5V
±
10%)
PARAMETER
SYMBOL
TYP
MAX
M10B11664A
UNIT
Input Capacitance (address)
Input Capacitance (
RAS
,
CASH
,
CASL
, WE ,
OE
)
Output capacitance (I/O0~I/O15)
C
I1
C
I2
C
I / O
-
-
-
5
7
10
pF
pF
pF
AC ELECTRICAL CHARACTERISTICS
(Ta = 0 to 70
°
C , V
CC
=5V
±
10%, V
SS
= 0V) (note 14)
Test Conditions
Input timing reference levels : 0V, 3V
Output reference level : V
OL
= 0.8V, V
OH
=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed t
T
= 2ns
PARAMETER
SYMBOL
-25
MIN
MAX
MIN
-30
MAX
MIN
-35
MAX
MIN
-40
MAX
UNIT Notes
Read or Write Cycle Time
Read Write Cycle Time
Fast-Page-Mode Read or Write Cycle Time
Fast-Page-Mode Read-Write Cycle Time
Access Time From
RAS
Access Time From
CAS
Access Time From
OE
Access Time From Column Address
Access Time From
CAS
Precharge
RAS
Pulse Width
RAS
Pulse Width (Fast Page Mode)
RAS
Hold Time
RAS
Precharge Time
CAS
Pulse Width
CAS
Hold Time
CAS
Precharge Time
RAS
to
CAS
Delay Time
CAS
to
RAS
Precharge Time
t
RC
t
RWC
t
PC
t
PCM
t
RAC
t
CAC
t
OAC
t
AA
t
ACP
t
RAS
t
RASC
t
RSH
t
RP
t
CAS
t
CSH
t
CP
t
RCD
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
AR
t
RAL
43
65
15
37
25
8
8
12
14
25
25
8
15
4
21
4
10
5
0
5
8
0
5
22
12
13
17
10,000
10,000
10,000
55
85
20
42
30
9
9
16
18
30
10,000
65
95
23
49
35
10
10
18
20
35
10,000
75
105
25
52
40
11
11
20
22
40
10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,000
ns
ns
ns
29
ns
ns
ns
ns
20
ns
ns
ns
ns
ns
8
18
18
19
23
7,18
19
24
20
22
22
4
5,20
13,20
30 100,000 35 100,000 40 100,000
9
20
9
30
5
10
5
0
5
8
0
5
26
16
14
21
10,000
10
23
10
35
6
10
5
0
5
8
0
5
30
18
17
25
10,000
11
25
11
40
7
10
5
0
5
8
0
5
34
20
Row Address Setup Time
Row Address Hold Time
RAS
to Column Address Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference to
RAS
)
Column Address to
RAS
Lead Time
Elite Memory Technology Inc
Publication Date
:
Nov. 2004
Revision
:
1.3
4/15
EliteMT
(Continued)
PARAMETER
SYMBOL
-25
-30
-35
M10B11664A
-40
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
Notes
Read Command Setup Time
Read Command Hold Time Reference to
CAS
Read Command Hold Time Reference to
RAS
RAS
to Output in Low-Z
t
RCS
t
RCH
t
RRH
t
CLZ
t
OFF1
t
OFF2
t
WCS
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
RWD
t
AWD
t
CWD
t
T
t
REF
t
RPC
t
CSR
t
CHR
t
OEH
t
ORD
t
CLCH
t
RSR
t
RHR
0
0
0
3
3
15
6
0
5
22
5
7
5
0
5
22
34
21
17
1.5
50
4
10
5
7
4
0
4
5
5
0
0
0
3
3
15
8
0
5
26
5
8
6
0
5
26
46
32
25
1.5
50
4
10
10
10
4
0
9
5
5
0
0
0
3
3
15
8
0
5
30
5
9
7
0
5
30
51
34
26
2.5
50
4
10
10
10
4
0
10
5
5
0
0
0
3
3
15
8
0
5
34
5
10
8
0
5
34
56
36
27
2.5
50
4
10
10
10
5
0
11
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
15,18
9,15,19
9
20
10,17,20
17,25
11,15,18
15,24
15
15
15
15,19
12,20
12,20
Output Buffer Turn-off Delay From
RAS
Output Buffer Turn-off to
OE
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time(Reference to
RAS
)
Write Command Pulse Width
Write Command to
RAS
Lead Time
Write Command to
CAS
Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to
RAS
)
RAS
to WE Delay Time
11
11
11,18
2,3
Column Address to WE Delay Time
CAS
to WE Delay Time
Transition Time (rise or fall)
Refresh Period (256 cycles)
RAS
to
CAS
Precharge Time
CAS
Setup Time(CBR REFRESH)
CAS
Hold Time(CBR REFRESH)
OE
Hold Time From WE During
Read-Modify-Write Cycle
OE
Setup Prior to
RAS
During Hidden Refresh
Cycle
1,18
1,19
16
Last
CAS
Going Low to First
CAS
Returning
High
Read Setup Time Reference to
RAS
in CBR
Read Hold Time Reference to
RAS
in CBR
21
Elite Memory Technology Inc
Publication Date
:
Nov. 2004
Revision
:
1.3
5/15
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