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NT1GT64UH8D0FS-AC

Description
DDR DRAM Module, 128MX8, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-200
Categorystorage    storage   
File Size2MB,25 Pages
ManufacturerNanya
Websitehttp://www.nanya.com/cn
Environmental Compliance
Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.
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NT1GT64UH8D0FS-AC Overview

DDR DRAM Module, 128MX8, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-200

NT1GT64UH8D0FS-AC Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNanya
Parts packaging codeDIMM
package instructionDIMM, DIMM200,24
Contacts200
Reach Compliance Codecompli
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time0.4 ns
Other featuresAUTO/SELF REFRESH; WD-MAX; SEATED HGT-NOM
Maximum clock frequency (fCLK)400 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N200
length67.6 mm
memory density1073741824 bi
Memory IC TypeDDR DRAM MODULE
memory width8
Number of functions1
Number of ports1
Number of terminals200
word count134217728 words
character code128000000
Operating modeSYNCHRONOUS
Maximum operating temperature65 °C
Minimum operating temperature
organize128MX8
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM200,24
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height30 mm
self refreshYES
Maximum standby current0.07 A
Maximum slew rate1.952 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch0.6 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.8 mm

NT1GT64UH8D0FS-AC Preview

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NT512T64UH4D0FN / NT1GT64UH8D0FN / NT2GT64U8HD0BN
NT512T64UH4D0FS / NT1GT64UH8D0FS / NT2GT64U8HD0BS
512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64
PC2-4200 / PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
Based on DDR2-533/667/800 64Mx16 (512MB)/64Mx16 (1GB)/128Mx8 (2GB) SDRAM D-Die
Features
• Performance:
Speed Sort
DIMM CAS Latency
fck – Clock Freqency
tck – Clock Cycle
fDQ – DQ Burst Freqency
PC2-4200
-37B
4
266
3.75
533
PC2-5300
-3C
5
333
3
667
PC2-6400
-AD
6
400
2.5
800
PC2-6400
-AC
5
400
2.5
800
MHz
ns
Mbps
Unit
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 512MB: 64Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx16
DDR2 SDRAM D Die devices.
• 1GB: 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx16
DDR2 SDRAM D Die devices.
• 2GB: 256Mx64 Unbuffered DDR2 SO-DIMM based on 128Mx8
DDR2 SDRAM D Die devices.
• Intended for 266MHz, 333MHz, and 400MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
DD
= V
DDQ
= 1.8V ± 0.1V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• Programmable Operation:
- DIMM
Latency: 3, 4, 5 (-37B/-3C/-AC)
- DIMM
Latency: 4, 5, 6 (-AD)
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• 13/10/1 Addressing (512MB)
• 13/10/2 Addressing (1GB)
• 14/10/2 Addressing (2GB)
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• 512MB/1GB module’s SDRAMs are 84-ball BGA Package
• 2GB module’s SDRAMs are 60-ball BGA Package
• RoHS compliance
• Halogen free product:
- NT512T64UH4D0FS
- NT1GT64UH8D0FS
- NT2GT64U8HD0BS
Description
NT512T64UH4D0FN, NT512T64UH4D0FS, NT1GT64UH8D0FN, NT1GT64UH8D0FS, NT2GT64U8HD0BN and NT2GT64U8HD0BS are
unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as
one rank (512MB)/two ranks (1GB/2GB) of 64Mx64 (512MB)/128Mx64 (1GB)/256Mx64 (2GB) high-speed memory array.
NT512T64UH4D0FN and NT512T64UH4D0FS use four 64Mx16 84-ball BGA packaged devices; NT1GT64UH8D0FN and
NT1GT64UH8D0FS use eight 64Mx16 84-ball BGA packaged devices; NT2GT64U8HD0BN and NT2GT64U8HD0BS use sixteen 128Mx8
60-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs.
The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SODIMMs provide a
high-performance, flexible 8-byte interface in a space-saving footprint.
The DIMM is intended for use in applications operating of 266MHz (333MHz or 400MHz) clock speeds and achieves high-speed data
transfer rates of 533Mbps (667Mbps or 800Mbps). Prior to any access operation, the device
latency and burst/length/operation type
must be programmed into the DIMM by address inputs A0-A12 (512MB/1GB)/A0-A13 (2GB) and I/O inputs BA0, BA1 and BA2 using the
mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are
programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.2
03/2008
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
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