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M13S2561616A-4BG2A

Description
DDR DRAM, 16MX16, 0.7ns, CMOS, PBGA60, 8 X 13 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-60
Categorystorage    storage   
File Size1MB,49 Pages
ManufacturerESMT
Websitehttp://www.esmt.com.tw/
Elite Semiconductor Memory Technology Inc. (ESMT) is a professional IC design company founded by Dr. Hu Zhao in June 1998. Its headquarters is located in Hsinchu Science Park, Taiwan. The company's main business includes research, development, manufacturing, sales and related technical services of IC products. It was listed on the Taiwan Stock Exchange in March 2002.
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M13S2561616A-4BG2A Overview

DDR DRAM, 16MX16, 0.7ns, CMOS, PBGA60, 8 X 13 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-60

M13S2561616A-4BG2A Parametric

Parameter NameAttribute value
MakerESMT
package instructionVFBGA,
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.7 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B60
length13 mm
memory density268435456 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals60
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX16
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Maximum seat height1 mm
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
width8 mm

M13S2561616A-4BG2A Preview

Download Datasheet
ESMT
DDR SDRAM
Features
Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Four bank operation
CAS Latency : 2, 2.5, 3, 4
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
M13S2561616A (2A)
4M x 16 Bit x 4 Banks
Double Data Rate SDRAM
All inputs except data & DM are sampled at the rising edge of the system clock (CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Data mask (DM) for write masking only
V
DD
= 2.5V
±
0.2V, V
DDQ
= 2.5V
±
0.2V
7.8us refresh interval
Auto & Self refresh
2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID
M13S2561616A -4TG2A
M13S2561616A -5TG2A
M13S2561616A -6TG2A
M13S2561616A -4BG2A
M13S2561616A -5BG2A
M13S2561616A -6BG2A
Max Freq.
250MHz (DDR500)
200MHz (DDR400)
166MHz (DDR333)
250MHz (DDR500)
200MHz (DDR400)
166MHz (DDR333)
2.5V
60 Ball BGA
66 pin TSOPII
Pb-free
V
DD
Package
Comments
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.4
1/49
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