PHPT610035PK
24 October 2014
PNP/PNP matched high power double bipolar transistor
Product data sheet
1. General description
PNP/PNP high power matched double bipolar transistor in a SOT1205 (LFPAK56D)
Surface-Mounted Device (SMD) power plastic package. Matched version of
PHPT610030PK.
NPN/NPN complement: PHPT610035NK.
2. Features and benefits
•
•
•
•
•
•
Current gain matching 10 %
High thermal power dissipation capability
Suitable for high temperature applications up to 175 °C
Reduced Printed-Circuit Board (PCB) requirements comparing to transistors in DPAK
High energy efficiency due to less heat generation
AEC-Q101 qualified
3. Applications
•
•
•
•
•
•
Current mirror
Motor control
Power management
Backlighting applications
Relay replacement
Differential amplifiers
4. Quick reference data
Table 1.
Symbol
Per transistor
V
CEO
I
C
Per transistor
R
CEsat
collector-emitter
saturation resistance
I
C
= -2 A; I
B
= -200 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02; T
amb
= 25 °C
-
110
180
mΩ
collector-emitter
voltage
collector current
open base
-
-
-
-
-100
-3
V
A
Quick reference data
Parameter
Conditions
Min
Typ
Max
Unit
Nexperia
PHPT610035PK
PNP/PNP matched high power double bipolar transistor
5. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
E1
B1
E2
B2
C2
C2
C1
C1
emitter TR1
base TR1
emitter TR2
base TR2
collector TR2
collector TR2
collector TR1
collector TR1
1
2
3
4
E1
B1
sym138
TR1
TR2
Simplified outline
8
7
6
5
Graphic symbol
C1
B2
E2
C2
LFPAK56D (SOT1205)
6. Ordering information
Table 3.
Ordering information
Package
Name
PHPT610035PK
LFPAK56D
Description
Plastic single ended surface mounted package (LFPAK56D); 8
leads
Version
SOT1205
Type number
PHPT610035PK
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
24 October 2014
2 / 16
Nexperia
PHPT610035PK
PNP/PNP matched high power double bipolar transistor
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Per transistor
V
CBO
V
CEO
V
EBO
I
C
I
CM
I
B
P
tot
collector-base voltage
collector-emitter voltage
emitter-base voltage
collector current
peak collector current
base current
total power dissipation
T
amb
≤ 25 °C
[1]
[2]
[3]
Parameter
Conditions
open emitter
open base
open collector
Min
-
-
-
-
Max
-100
-100
-8
-3
-8
-0.5
1
2.4
25
1.25
3
5
175
175
175
Unit
V
V
V
A
A
A
W
W
W
W
W
W
°C
°C
°C
single pulse; t
p
≤ 1 ms
-
-
-
-
-
-
-
-
-
-55
-65
Per device
P
tot
total power dissipation
T
amb
≤ 25 °C
[1]
[2]
[4]
T
j
T
amb
T
stg
junction temperature
ambient temperature
storage temperature
[1]
[2]
[3]
[4]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm .
Power dissipation from junction to mounting base.
Device mounted on a ceramic PCB, Al
2
O
3
, standard footprint.
2
PHPT610035PK
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
24 October 2014
3 / 16
Nexperia
PHPT610035PK
PNP/PNP matched high power double bipolar transistor
4
P
tot
(W)
3
aaa-014341
(1)
2
1
(2)
0
-75
0
2
75
150
225
T
amb
(°C)
(1) FR4 PCB, mounting pad for collector 6 cm
(2) FR4 PCB, standard footprint
Fig. 1.
Per transistor: power derating curves
8. Thermal characteristics
Table 5.
Symbol
Per transistor
R
th(j-a)
thermal resistance
from junction to
ambient
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
[1]
[2]
[3]
Thermal characteristics
Parameter
Conditions
in free air
[1]
[2]
Min
-
-
-
Typ
-
-
-
Max
150
62.5
6
Unit
K/W
K/W
K/W
R
th(j-sp)
Per device
R
th(j-a)
in free air
[1]
[2]
[3]
-
-
-
-
-
-
120
50
30
2
K/W
K/W
K/W
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm .
Device mounted on a ceramic PCB, Al
2
O
3
, standard footprint.
PHPT610035PK
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
24 October 2014
4 / 16
Nexperia
PHPT610035PK
PNP/PNP matched high power double bipolar transistor
10
3
Z
th(j-a)
(K/W)
10
2
0.75
0.33
0.2
10
0.05
0.01
1
aaa-014342
duty cycle = 1
0.5
0.25
0.1
0.02
0
10
-1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig. 2.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
10
2
Z
th(j-a)
(K/W)
10
0.75
0.33
0.2
aaa-014343
duty cycle = 1
0.5
0.25
0.1
0.05
0.02
0
1
0.01
10
-1
10
-5
10
-4
10
-3
10
-2
2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, mounting pad for collector 6 cm
Fig. 3.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
PHPT610035PK
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
24 October 2014
5 / 16
Embedded System
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