Product Specification
PE97022
Product Description
Peregrine’s PE97022 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.5 GHz. The device
is designed for superior phase noise performance while
providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
The PE97022 features a ÷10/11 dual modulus prescaler,
counters and a phase comparator as shown in
Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hardwired.
The PE97022 is optimized for commercial space
applications. Single Event Latch-up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10
-9
errors per bit / day. It is manufactured on Peregrine’s
UltraCMOS
®
process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
Figure 1. Block Diagram
3.5 GHz UltraCMOS
®
Integer-N PLL
Rad Hard for Space Applications
Features
Low Power - 45 mA at 3.3 V
3.5 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector
Serial, parallel, or direct hardwired
mode
Ultra-Low Phase Noise: -216 dBc/Hz
SEU < 10 errors / bit-day
100 Krad (Si) total dose
Pin compatible with the PE9702,
-9
packaged in a 44-lead CQFJ
(reference application note AN22 at
www.psemi.com)
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©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 14
PE97022
Product Specification
Figure 2. Pin Configurations (Top View)
GND
GND
GND
V
DD
Enh
R
3
R
2
R
1
R
0
LD
fr
Figure 3. Package Type
44-lead CQFJ
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Pin Name
V
DD
R
0
R
1
R
2
R
3
GND
D
0
M
0
D
1
M
1
D
2
M
2
D
3
M
3
11
12
V
DD
V
DD
S_WR
13
D
4
M
4
Parallel
Direct
Input
Input
Interface Mode
ALL
Direct
Direct
Direct
Direct
ALL
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
Serial
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Type
(Note 1)
Input
Input
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing recommended.
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing recommended.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary
register data is transferred to the secondary register on S_WR or Hop_WR rising
edge.
Parallel data bus bit4
M Counter bit4
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 14
FSELP, A
0
E_WR, A
1
M2_WR, A
2
Smode, A
3
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
F
in
Document No. 70-0235-07
│
UltraCMOS
®
RFIC Solutions
PE97022
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
Sdata
14
D
5
M
5
Sclk
15
D
6
M
6
FSELS
16
D
7
Pre_en
17
GND
FSELP
18
A
0
Direct
Serial
E_WR
19
A
1
M2_WR
20
A
2
Smode
21
A
3
22
23
24
25
26
Bmode
V
DD
M1_WR
A_WR
Hop_WR
Direct
ALL
ALL
Parallel
Parallel
Serial, Parallel
Input
Input
(Note 1)
Input
Input
Input
Direct
Serial, Parallel
Input
Input
Parallel
Direct
Parallel
Input
Input
Input
Input
Input
Interface Mode
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
ALL
Parallel
Input
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS = 1) or secondary register (FSELS = 0)
for programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F
in
bypasses the prescaler.
Ground.
Selects contents of primary register (FSELP=1) or secondary register (FSELP = 0)
for programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode = 0, Smode = 1) or Parallel Interface Mode
(Bmode = 0, Smode = 0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode
= 1).
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
M1 write. D[7:0] are latched into the primary register (Pre_en
,
M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
Prescaler input from the VCO, 3.5 GHz max frequency. A 22 pF coupling capacitor
should be placed as close as possible to this pin and terminated with a 50
Ω
resistor
to ground.
Prescaler complementary input. A 22 pF bypass capacitor should be placed as close
as possible to this pin and be connected in series with a 50
Ω
resistor to ground.
Ground.
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 31.
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 14
27
F
in
ALL
Input
28
29
30
F͞
in
GND
f
p
ALL
ALL
ALL
Input
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│
www.psemi.com
PE97022
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin Name
V
DD
-f
p
Dout
V
DD
C
EXT
V
DD
PD_U
PD_U
V
DD
-f
c
f
c
GND
GND
f
r
LD
Enh
Interface Mode
ALL
Serial, Parallel
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial, Parallel
Input
Output
Input
(Note 1)
Output
Type
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
Description
V
DD
for f
p
. Can be left floating or connected to GND to disable the f
p
output.
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series
resistor. Connecting C
EXT
to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
PD_D is pulse down when f
p
leads f
c
.
PD_U is pulse down when f
c
leads f
p
.
V
DD
for f
c
. Can be left floating or connected to GND to disable the f
c
output.
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 38.
Ground.
Ground.
Reference frequency input.
Lock detect and open drain logical inversion of C
EXT
. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Notes: 1. V
DD
pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
V
DD
pins 31 and 38 are used to enable test modes and should be left floating.
2. All digital input pins have 70 kΩ pull-down resistors to ground.
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 14
Document No. 70-0235-07
│
UltraCMOS
®
RFIC Solutions
PE97022
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature
range
Min
-0.3
-0.3
-10
-10
-65
Max
4.0
V
DD
+ 0.3
+10
+10
150
Units
V
V
mA
mA
°C
Table 4. ESD Ratings
Symbol
V
ESD
Parameter/Conditions
ESD voltage (Human Body Model)
1
Level
1000
Units
V
Note: 1. Periodically sampled, not 100% tested. Tested per MIL-STD-
883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in
Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.45
85
Units
V
°C
Table 5. DC Characteristics:
V
DD
= 3.3 V, -40 °C < T
A
< 85 °C, unless otherwise specified
Symbol
Parameter
Operational supply current;
I
DD
Prescaler disabled
Prescaler enabled
Digital Inputs: All except f
r
, F
in
, F
in
V
IH
V
IL
I
IH
I
IL
Reference Divider input: f
r
I
IHR
I
ILR
High level input current
Low level input current
V
IH
= V
DD
= 3.45 V
V
IL
= 0, V
DD
= 3.45 V
-100
100
μA
μA
High level input voltage
Low level input voltage
High level input current
Low level input current
V
DD
= 2.85 to 3.45 V
V
DD
= 2.85 to 3.45 V
V
IH
= V
DD
= 3.45 V
V
IL
= 0, V
DD
= 3.45 V
-1
0.7 x V
DD
0.3 x V
DD
70
V
V
μA
μA
V
DD
= 2.85 to 3.45 V
15
45
50
mA
mA
Conditions
Min
Typ
Max
Units
Counter and phase detector outputs: f
c
, f
p
.
V
OLD
V
OHD
Output voltage LOW
Output voltage HIGH
I
out
= 6 mA
I
out
= -3 mA
V
DD
- 0.4
0.4
V
V
Lock detect outputs: C
EXT
, LD
V
OLC
V
OHC
V
OLLD
Output voltage LOW, C
EXT
Output voltage HIGH, C
EXT
Output voltage LOW, LD
I
out
= 100
μA
I
out
= -100
μA
I
out
= 1 mA
V
DD
- 0.4
0.4
0.4
V
V
V
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©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
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