How to prevent sharing conflicts in dual-port RAM

eeleader

How to prevent sharing conflicts in dual-port RAM [Copy link]

Generally, dual-port RAM provides two completely independent ports, each of which has its own control line, address line and data line. The CPU's operation on the dual-port RAM port is equivalent to operating its external RAM. The problem that needs to be paid attention to in the use of dual-port RAM is how to avoid the contention of the CPUs at both ends for the same RAM unit. Generally speaking, dual-port RAM can provide three anti-collision methods, which are explained below in conjunction with CY7C144 of CYPRESS. CY7C144 is a dual-port static RAM with 8×8k-bit capacity and high-speed access (20ns) produced by low-power CMOS process. It can also use multi-chip cascading to expand the word width. Its internal principle block diagram is shown in Figure 1. 2.1 Anti-collision method of inserting wait state When the left and right ports access the RAM storage unit of the same address at the same time, the arbitration unit inside the CY7C144 chip will give a BUSY signal. Specifically, the normal state of the BUSYL and BUSYR signals is high level. When the left port accesses a storage unit, if the right port also operates the storage unit, the arbitration unit inside the chip will make the signal BUSYR low until the left port operation is completed and then restore BUSYR to high level. In the design, the BUSY signal can be used as the wait state input of the CPU, and the signal can be used to insert the wait state during the operation of the CPU to avoid both ends from operating the dual-port RAM at the same time. 2.2 Semaphore anti-collision method The dual-port RAM can avoid conflicts by applying for and releasing the port's semaphore (also called token) to operate the storage unit. One semaphore corresponds to a corresponding number of storage units. Both ends of the dual-port RAM can access the semaphore. When the left port writes "0" to the signal light and then reads back the signal light, if the signal light is also "0", it means that the left port has control over the storage unit, otherwise it means that the right port has control over the storage unit. Regardless of whether the control over the storage unit is obtained, "1" should be written to the signal light after the operation is completed to release the signal, so as to avoid resource deadlock. The CY7C144 chip provides 8 signal lights, and the storage unit of each signal light is 8×2k bits. When operating the signal light, the chip select signal (CEL, CER) should be high level, and the signal light enable signal (SEML, SEMRR) should be low level. A0~A2 represents the address of the signal light, and the lowest bit of the data line I/O0 represents the value of the signal light. The general process of accessing the storage unit is shown in Figure 2. 2.3 Interrupt anti-collision mode The two storage units with the highest addresses in the dual-port RAM can be used as mailboxes, and the left and right ends can operate it at the same time. The highest address is the mailbox of the right port, and the second highest address is the mailbox of the left port. Taking the CY7C144 chip as an example, the offset address 1FFEH is the left port mailbox, and the offset address 1FFFH is the right port mailbox. When the right port writes to the left port mailbox 1FFEH, the signal INTL of the left port will become low, and when the left port reads its own mailbox 1FFEH, the signal INTL will be high again; similarly, when the left port writes to the right port mailbox 1FFFH, the signal INTR of the right port will become low, and when the right port reads its own mailbox 1FFFH, the signal INTR will be high again. The signals INTL and INTR can be used as the interrupt source of the CPU, and the state of using the storage unit can be transmitted to the other party through the mailbox to achieve the purpose of preventing conflicts. 2.4 Comparison of three anti-collision methods Among the above three methods, the method of inserting the wait state will affect the data transmission rate for the high-speed interface, and requires the CPU to have the function of inserting the wait state, while some CPUs (such as 8031) do not have this function. The semaphore method is mainly used when two CPUs share memory space. If the dual-port RAM is mainly used to exchange data between the two CPUs, the real-time performance of the exchange is difficult to ensure by software. The interrupt method just solves this problem.

eeleader

Classic! Commonly used! :congratulate: