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Can any expert help me simulate this program first? I have homework to hand in and it's too late! [Copy link]

我还没学会仿真啊。就是一个序列检测器!谢谢大家啦!要WORD版的,截图放在WORD里!


library ieee;
use ieee.std_logic_1164.all;
entity  test_code is
port ( clk,reset :  in  std_logic;
        st_input:   in  std_logic;
       st_outputs:   out  std_logic
       );
end  test_code;
architecture  ar_test_code  of  test_code  is  
type  my_st  is  (s0,s1,s2,s3,s4,s5,s6,s7);
signal  current_st,next_st :  my_st;
begin  
process(clk,reset)
begin
if  (clk'event  and  clk='1')  then
current_st<=next_st;
end  if;
end  process;
process( current_st, st_input)
begin
  st_outputs<='0';
case  current_st  is
  when  s0=>   if  st_input='0'  then   next_st<=s0;
else next_st<=s1;
end  if;
when  s1=>  if  st_input='1'   then  next_st<=s2;
else  next_st<=s0;
end  if ;
  when  s2=>  if  st_input='1'  then  next_st<=s3;
else next_st<=s0;
end  if;
  when  s3=>  if  st_input='0'  then  next_st<= s4;
else  next_st<=s3;
end  if;
   when  s4=>  if  st_input='0'  then   next_st<=s5;
   else next_st<=s1;
end  if;
   when  s5=>  if  st_input='1'  then  next_st<=s6;
  else  next_st<=s0;
end  if;
  when  s6=>  if  st_input='0'   then  next_st<=s7;  st_outputs<='1';
  else  next_st<=s2;
end  if;
  when s7=> if st_input='1'   then  next_st<=s0;
  else  next_st<=s1;
   end if;
end  case;
end  process;
end  ar_test_code;
This post is from FPGA/CPLD

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The code is a shift register plus a judgment, and there is no need to use a state machine. But the complete code needs to be done as mentioned on the second floor.  Details Published on 2012-3-7 09:58

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Asking others to do it for you, no one wants to do it! Here are the specific steps: 1. Create a project; 2. Create a .vhd file; 3. Compile 4. Create a waveform file, add input and output 5. Simulate and output the results I am online at QQ: 932295949, you can ask me anytime if you have any questions [ This post was last edited by Sea_eeworld on 2010-5-8 14:00 ]
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Personal signature快乐是一天,不快乐也是一天,为什么不天天快乐呢

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For a sequence detector, a simple method is to write it in one sentence of HDL language, without making it as complicated as the above.
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Personal signature一个为理想不懈前进的人,一个永不言败人!
http://shop57496282.taobao.com/
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Could you please tell me how this can be solved with just one sentence? :)
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Personal signature有目的的学习是最有效的学习!

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How to solve this problem? Please help!
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Help you to prevent it,, package error ERROR:HDLCompiler:1156 - "D:/kkkkkkkkkkkk/jjj/ttyyty.vhd" Line 43: Formal port does not exist in entity .  Please compare the definition of block to its component declaration and its instantion to detect the mismatch.
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit ttyyty in library work failed
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The simulation result after deleting the RESET signal. I'll give you the picture.

jr.JPG (130.77 KB, downloads: 1)

jr.JPG
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Haha, I have also done the sequence detection, but I don’t know much about setting the frequency of simulation. I spent a long time on it... It is still faster to connect to the hardware detection.
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What sequence do you want to detect?
This post is from FPGA/CPLD
Personal signature一个为理想不懈前进的人,一个永不言败人!
http://shop57496282.taobao.com/
欢迎光临网上店铺!

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The code is a shift register plus a judgment, and there is no need to use a state machine. But the complete code needs to be done as mentioned on the second floor.
This post is from FPGA/CPLD

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