Can any expert help me simulate this program first? I have homework to hand in and it's too late!

870027359

Can any expert help me simulate this program first? I have homework to hand in and it's too late! [Copy link]

我还没学会仿真啊。就是一个序列检测器！谢谢大家啦！要WORD版的，截图放在WORD里！


library ieee;
use ieee.std_logic_1164.all;
entity  test_code is
port ( clk,reset :  in  std_logic;
        st_input:   in  std_logic;
       st_outputs:   out  std_logic
       );
end  test_code;
architecture  ar_test_code  of  test_code  is  
type  my_st  is  (s0,s1,s2,s3,s4,s5,s6,s7);
signal  current_st,next_st :  my_st;
begin  
process(clk,reset)
begin
if  (clk'event  and  clk='1')  then
current_st<=next_st;
end  if;
end  process;
process( current_st, st_input)
begin
  st_outputs<='0';
case  current_st  is
  when  s0=>   if  st_input='0'  then   next_st<=s0;
else next_st<=s1;
end  if;
when  s1=>  if  st_input='1'   then  next_st<=s2;
else  next_st<=s0;
end  if ;
  when  s2=>  if  st_input='1'  then  next_st<=s3;
else next_st<=s0;
end  if;
  when  s3=>  if  st_input='0'  then  next_st<= s4;
else  next_st<=s3;
end  if;
   when  s4=>  if  st_input='0'  then   next_st<=s5;
   else next_st<=s1;
end  if;
   when  s5=>  if  st_input='1'  then  next_st<=s6;
  else  next_st<=s0;
end  if;
  when  s6=>  if  st_input='0'   then  next_st<=s7;  st_outputs<='1';
  else  next_st<=s2;
end  if;
  when s7=> if st_input='1'   then  next_st<=s0;
  else  next_st<=s1;
   end if;
end  case;
end  process;
end  ar_test_code;

Sea_eeworld

Asking others to do it for you, no one wants to do it! Here are the specific steps: 1. Create a project; 2. Create a .vhd file; 3. Compile 4. Create a waveform file, add input and output 5. Simulate and output the results I am online at QQ: 932295949, you can ask me anytime if you have any questions [ This post was last edited by Sea_eeworld on 2010-5-8 14:00 ]

eeleader

For a sequence detector, a simple method is to write it in one sentence of HDL language, without making it as complicated as the above.

zqzq501311

Could you please tell me how this can be solved with just one sentence? :)

870027359

How to solve this problem? Please help!

pyy1980

Help you to prevent it,, package error ERROR:HDLCompiler:1156 - "D:/kkkkkkkkkkkk/jjj/ttyyty.vhd" Line 43: Formal port does not exist in entity .  Please compare the definition of block to its component declaration and its instantion to detect the mismatch.
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit ttyyty in library work failed

pyy1980

The simulation result after deleting the RESET signal. I'll give you the picture.

emnqsu

Haha, I have also done the sequence detection, but I don’t know much about setting the frequency of simulation. I spent a long time on it... It is still faster to connect to the hardware detection.

eeleader

What sequence do you want to detect?

myxxyy

The code is a shift register plus a judgment, and there is no need to use a state machine. But the complete code needs to be done as mentioned on the second floor.