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[SynPlify technical issue] Ask: Blackbox name problem in the integrated netlist [Copy link]

I have a module a, which only instantiates b and c without other logic. b and c are selected through conditional compilation
. Synpliify uses a as the name of the blackbox in the synthesized netlist, but I want to use b or c as the name of the blackbox.
Is there any way to do this? Thank you.
This post is from FPGA/CPLD

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jyl
The instantiation name can be directly represented by b or c, without a. Then, when synthesizing the netlist, you can see that it is actually b or c.  Details Published on 2010-7-22 09:24
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The instantiation name can be directly represented by b or c, without a. Then, when synthesizing the netlist, you can see that it is actually b or c.

This post is from FPGA/CPLD

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