I encountered a strange problem again: the amplitude of the crystal oscillator on the FPGA board dropped.

qd0090

I encountered a strange problem again: the amplitude of the crystal oscillator on the FPGA board dropped. [Copy link]

I encountered a strange problem again: the amplitude of the crystal oscillator on the FPGA board dropped, causing the FPGA to not work.

The board is easy to use. I have no problem using other programs, but a certain program causes the 4Vp-p crystal to change to 1Vp-p.

I am using Xilinx's Spartan 3 A. After I removed the chipscope from the program, the clock returned to normal. Then I added the chipscope again and the clock dropped to 1V again.

I slightly modified the program with chipscope (synchronized the external signal with clk), and the clock returned to normal. (I personally think this has nothing to do with the failure of the clock)

I am using ise 13.1. I had this problem before when I used ise 11.1. I didn't find the cause at that time, so I just took out all the vhd files in the design and rebuilt the design.

Has anyone encountered the same problem? How did you solve it?

eeleader

If you really have this problem, it means that the chip has a design flaw!

qd0090

I will send the project file, please help me take a look.

I packaged the project file in the attachment. This project is very simple, which is to debug the UART serial port program. Its function is that when the host computer sends a hexadecimal number "M" through the serial port, the FPGA will return "M+1", "M+2". ... until "M+i" = A0.
The attachment also uses a vhd file. When this file is used to replace the file with the same name in the project, the amplitude of the crystal oscillator returns to normal. (The attached picture shows the debugging result)
Thank you very much! for_fix_clk_bug.rar (1022.59 KB, downloads: 2)

2011-6-13 14:05 上传

点击文件名下载附件

eeleader

From a hardware perspective, the program cannot affect the amplitude of the clock.

qd0090

The problem is solved. I asked the engineer of Xilinx, haha, I benefited a lot. Thanks to Mr. Zhu!

The problem is that I set the chipscope's clk to the output of the dcm, which is wrong. It should be connected to the clock tree.

The output of the dcm is connected to the clock tree through a BUFG.

Although I still don't quite understand why it affects the crystal oscillator amplitude, after correcting this problem, the board does work properly.

常见泽1

Just help me solve it.