【Low Power Consumption】Power Consumption Analysis at 40nm and 45nm Process Nodes

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【Low Power Consumption】Power Consumption Analysis at 40nm and 45nm Process Nodes [Copy link]

At the 40nm and 45nm process nodes, power consumption has become the number one factor in FPGA selection. This white paper reveals how Xilinx designed the latest Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families to reduce dynamic power consumption more than their previous generation Spartan-3A and Virtex-5 devices. Such a significant reduction in power consumption requires a lot of engineering innovation. At the 40nm and 45nm nodes, transistor leakage current increases exponentially, making static power consumption a major challenge. In addition, the pursuit of high performance drives core clock frequencies higher, which increases dynamic power consumption. This white paper reveals how Xilinx has solved these challenges through engineering innovation on Spartan-6 and Virtex-6 FPGAs.

40nm与45nm工艺节点下的功耗分析.pdf (1.59 MB, downloads: 32)

2011-10-26 22:47 上传

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