This post was last edited by freebsder on 2014-8-15 21:59 1. The UNIFY bit in the CONFIG register sets whether the timer is used as one 32-bit or two 16-bit timers. Set this bit before accessing other registers. - UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
2. The REGMODEn bits in the REGMODE register set whether each pair of Match/Capture registers is used for match or capture. REGMODEn= 1: Registers operate as match and reload registers. | CONFIG | UNIFY：0 | 0: 16-bit timer, 1: 32-bit timer | 0 | | | CLKMODE: 2:1 | 0: system clock, 1: prescaled system clock 2: SCT input, 3: pre-scaling SCT input | 00 | | | CKSEL: 6: 3 | 0: rising edge of input 0, 1: falling edge of input 0 2: rising edge of input 1, 3: falling edge of input 1 ...... E: 7 F: 7 | 0000 | | | NORELAOD_L：7 | Write 1 When a match occurs, reload from the reload register is prohibited. Software can read and write at any time. Both 16-bit and 32-bit timers are valid | 0 | | | NORELOAD_H：8 | Same as above, only valid at 16 bits | 0 | | | INSYNC: 16: 9 | Synchronize with SCT clock before generating event (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7, invalid when CLKMODE is 2 or 3) | 1 | | AUTOLIMIT_L: 17 When written as 1, a match event on the match0 register automatically becomes a LIMIT condition without explicitly defining an event. Software can read and write at any time. | 0 | | | AUTOLIMIT_H: 18 | Same as above, invalid for 16 bits. | 0 | | CTRL CONFIG:When UNIFY＝1, only those bits of _L are valid All bits can be written in STOP or HALT state, and only STOP or HALT bits can be written during operation Note: When CONFIG:CLKMODE=3, wait for at least 12 system clocks between consecutive writing of H or L or two consecutive writings | DOWN_L ：0 | Write 1 to count down. When the count limit is reached and BIDIR＝1, the hardware sets this bit to 1. When the count reaches 0 or the limit condition is met when counting down, the hardware sets this bit to 0. | 0 | | | STOP_L：1 | When HALT＝0, set to write 1, the counter stops working but can respond to IO. If the event in the Start register matches, this bit is cleared and the counter resumes working. | 0 | | | HALT_L ：2 | Write 1 to stop the counter from responding. When HALT＝1, STOP is cleared. To clear HALT but keep the counter responding, set HALT and STOP in one write instruction. Once HALT is set, it can only be cleared by software. | 1 | | | CLRCTR_L: 3 | Write 1 to clear the current counter. Always read as 0. | 0 | | | BIDIR_L ：4 | 0: The counter counts up to the limit and then clears to 0, 1: The counter counts up to the limit and then counts down to 0 or the limit condition occurs | 0 | | | PRE_L：12：5 | SCT clock pre-scaling factor. Count clock = SCTClock/(PRE+1). Once the PRE pre-scaling factor is changed, the CLRCTR counter needs to be cleared. | 0 | | | DOWN_H：16 STOP_H：17 HALT_H：18 CLRCTR_H：19 BIDIR_H：20 PRE_H ：28：21 | | | | LIMIT | LIMMSK_L：15：0 LIMMSK_H：31：16 Event n is used as the counting limit event. When the count reaches the limit, the counter is cleared to 0 (unidirectional counting mode) or the counting direction is changed (bidirectional counting mode). If the counter reaches the maximum value (0xffff/0xffffffff), even if the limit condition is not set in the LIMIT register, the counter will be cleared to 0 or the counting direction will be changed on the next clock edge L: event 0 = bit 0, event 1 = bit 1, event 15 = bit 15 H: event 0 = bit 16, event 1 = bit 17, event 15 = bit 31 | 0 | | HALT | HALTMSK_L：15：0 HALTMSK_H ：31:16 | Bit n writes 1, set CTRL when event n occurs:HALT 对应的位 L：event 0 = bit 0, event 1 = bit 1, event 15 = bit 15 H：event 0 = bit 16, event 1 = bit 17, event 15 = bit 31 | 0 | | STOP | STOPMSK_L：15：0 STOPMSK_H：31：16 | bit n 写1，事件n发生时设置 CTRL:STOP 对应的位 L：event 0 = bit 0, event 1 = bit 1, event 15 = bit 15 H：event 0 = bit 16, event 1 = bit 17, event 15 = bit 31 | 0 | | START | STARTMSK_L：15：0 STARTMSK_H：31：16 | bit n 写1，事件n发生时清除 CTRL:STOP 对应的位。（HALT＝1时不能产生事件，所以清除HALT位的事情只能由软件写） L：event 0 = bit 0, event 1 = bit 1, event 15 = bit 15 H：event 0 = bit 16, event 1 = bit 17, event 15 = bit 31
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| | COUNT | CTR_L：15：0 CTR_H：31：16 | 软件可随时读，但只能在HALT＝1时写。 |
| | STATE | STATE_L：4：0 STATE_H：20：16 | 软件可随时读，但只能在HALT＝1时写。事件可配置为在某些状态发生。事件完成以下任务： 设置或者清除输出信号 设置计数器 limit, stop, 和 start 引发中断和DMA请求 修改state变量 The state value is completely controlled by the application. If the application does not need state, this value is the default value 0 The state variable can track and control the counter in any desired operation order for multiple cycles. The state variable is logically associated with the state machine configured by the SCT. For the relationship between state and event, refer to Sections 15.6.26 and 15.6.27. The STATELD/STADEV fields in all EVENT control registers (n) set all possible values for the state variable. Changes in the state variable during the counting cycle reflect the state changes of the state machine. | 0 | | INPUT | AIN0-7;SIN0-7 | Read input status AIN: SCT Clock sampling SIN: SCT clock sampling after INSYNC selection | - | | REGMODE | REGMOD_L:15:0 REGMOD_H:31:16 | There are 16 pairs of Match/Capture registers When used as a match function, there are auxiliary registers to reload the count value, and when used as a capture function, there are also auxiliary registers to control the capture. 0/1: match/capture L: register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15 H：register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31 | 0 | | OUTPUT OUTPUT：9：0 OUT：9：0 Supports 10 outputs. When HALT＝1, writing this register can directly control the output. It can be read at any time. 0/1：LOW/HIGH output 0 = bit 0, output 1 = bit 1,..., output 9 = bit 9 | 0 | | OUTPUTDIRCTRL | SETCLR0：1：0 …… SETCLR9:19:18 | Sets or clears on output n (0-9). 0x0: No setting or clearing occurs on any counter 0x1: Invert the set and clear states when the L counter or unified counter starts counting down. 0x2: Invert the set and clear states when the H counter starts counting down. Do not use when UNIFY＝1. | 0 | | RES | O0RES：1：0 …… O9RES：19：18 | OUTn_SET and OUTn_CLR can control the output state at the same time, even in the same state. This register is used to handle this contradictory state. If the output needs to be inverted in a certain state, OnRES can be set to 0x3, and the event flag bit can be set in the Set and Clear registers. 0x0 The output is unchanged 0x1 The output is set (or cleared depending on the setting of the SETCLR field). 0x2 The output is cleared (or set depending on the setting of the SETCLR field). 0x3 The output is inverted | 0 | | DMAREQ0 DMAREQ1 | DEV_0：15：0 DRL0：30 DRQ0：31 | | | | EVEN IEN：15：0 Enable interrupt at event n. Used with EVFLAG. | 0 | | EVFLAG | FLAG:15:0 | Record the events that occurred. Write 1 to clear the corresponding flag bit. If all flag bits that enable interrupts are cleared to 0, the SCT interrupt request is eliminated. | 0 | | CONEN | NCEN: 9:0 | When a conflict occurs (RES), an interrupt is generated output 0 = bit 0, output 1 = bit1,..., output 9 = bit 9 | 0 | | CONFLAG | NCFLAG：9：0 BUSERRL：30 BUSERRH：32 [/ td] [td] | 0 | | MATCH[0:15] [/ td] [td] MATCHn_L：15：0 MATCHn_H：31：16 Match register is compared with counter to generate events. Can only be written when HALT=1, can be read at any time. Count to match value Clear to 0 or count down. | | | FRACMAT [0:5] | | | | | CAP[0:15] | [ font=SimSun]CAPn_L：15:0 CAPn_H：31:16 | When an event occurs, it is used to read the captured count value | | | MATCHREL[0:15] [/ td] [td] RELOADn_L ：15：0 [size =12.0pt]RELOADn_H ：31：16 | When BIDIR=0, limit After the condition occurs, the MATCH[0:15] register value is loaded from here. When BIDIR=1, the counter Returns to 0 when loaded. | | | FRACMATREL [0:5] | | | | | CAPCTRL[0:15] | [align= left]CAPCONn_L CAPCONn_H | Set which events are used to capture the counter value and store it in the CAPn_LH register | [/td ] [/tr] | | EV[0:15]_STATE [/td] STATEMSKn：15：0 | [font =SimSun]Set the states in which the event occurs. The states are set in EVn_CTRL. If the masks in EVn_STATE corresponding to event n are all 0, the event is disabled. In applications that do not need state but need event, this register is written to 0x01, and the state remains at the default setting of 0. pt]State bit m is set, and event event n (0-15) is triggered in this state. (m = state number; state 0 = bit 0, state 1 = bit 1,..., state 15 = bit 15) | 0 [/ td] [/tr] | | EV[0:15]_CTRL [/td ] [td] MATCHSEL:3:0 | Selects which Match register's match triggers the event. (Only the counter set by HEVENT will have a match.) | 0 | | Together with the state mask, sets the conditions for event n to occur. HEVENT：4 Select L/H counter. Do not set this bit when UNIFY＝1. 0: L state and L match register selected by MATCHSEL 1: H | 0 | | The event is triggered by the match event, and can also be triggered by the selected input signal (edge or level). When BIDR＝1, it can also be triggered when the count is reversed. | OUTSEL: 5 | Select Input/output 0: Select the input configured by IOSEL 1: Select the output configured by IOSEL | 0 | | Each event can modify the STATE value (state migration). IOSEL: 9: 6 Configure the input or output signal that triggers the event. Do not select input if CKMODE = 1x. | 0 | | If multiple events are configured to occur when the counting condition is met, the change in the state value will only affect the highest-numbered event, and the actions configured for each event will all occur. | IOCOND:11:10 | Configure the IO condition that triggers event n. 0x0 LOW low level 0x1 Rise rising edge 0x2 Fall falling edge 0x3 HIGH high level | 0 | | | COMBMODE：13：12 | Configure the use and combination of match and IO conditions 0x0 OR. The event occurs when the match or io condition is met. 0x1 MATCH. Only when the match condition is met. 0x2 IO. Only when the IO condition is met. 0x3 AND.The match and IO conditions are met at the same time. | 0 | | | STATELD: 14 | Configure the way STATEV modifies the state set by HEVENT (the state modification occurs when the event is the highest-numbered event). 0 The value of STATEV is added to STATE. (Carry is discarded)1 The value of STATEV is loaded directly into STATE.00STATEV：19：15STATEV：19：15 The state value or state increment is determined by STATELD. If STATELD and STATEV are both 0, the value of STATE does not change. | 0 | | | MATCHMEM：20 | If this position is 1, and COMBMODE is set with a match condition, the event will be triggered as long as the counting condition is greater than or equal to the match setting when counting up, and less than or equal to the counting condition when counting down. If this position is 0, the match event will only occur in the clock cycle that is equal to the match value. | - | | | DIRECTION：22：21 | The relationship between the occurrence of the event and the counting direction. Only valid in BIDIR＝1 mode. 0x0 The counting direction is irrelevant. The occurrence of this event is irrelevant to the counting direction. 0x1 Counting upwards. This event occurs only when counting up. 0x2 Counting down. This event occurs only when counting down. | - | | OUT[0:9]_SET | SET:15:0 | If position n is 1, event n sets output n, or clears it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 | | | OUT[0:9]_CLR | CLR:15:0 | If position n is set, event n clears output n, or sets it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 | |
0pt]STATELD：14 [/td] [td] Configures the way STATEV modifies the state set by HEVENT (the state modification occurs when this event is the highest-numbered event). 0 The value of STATEV is added to STATE. (The carry is discarded) 1 The value of STATEV is directly loaded into STATE. [/td] [td] 0 [/td] [/tr] [tr] [td] [/td] [td] STATEV:19:15 [/td] [td] The state value or state increment is determined by STATELD. If STATELD and STATEV are both 0, the STATE value does not change. [/td] [td] 0 [/td] [/tr] [tr] [td] [/td] [td] MATCHMEM：20 [/td] [td] If this position is 1, and COMBMODE is set with a match condition, the event will be triggered as long as the counting condition is greater than or equal to the match setting when counting up, and less than or equal to the counting condition when counting down. If this position is 0, the match event will only occur in the clock cycle that is equal to the match value. [/td] [td] - [/td] [/tr] [tr] [td] [/td] [td] DIRECTION：22：21 [/td] [td] The relationship between the occurrence of the event and the counting direction. Only valid in BIDIR＝1 mode. 0x0 The counting direction is irrelevant. The occurrence of this event is irrelevant to the counting direction. 0x1 Counting upwards. This event occurs only when counting up. 0x2 Counting down. This event occurs only when counting down. [/td] [td] - [/td] [/tr] [tr] [td] OUT[0:9]_SET [/td] [td] SET:15:0 [/td] [td] If position n is 1, event n sets output n, or clears it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [tr] [td] OUT[0:9]_CLR [/td] [td] CLR:15:0 [/td] [td] If position n is set, event n clears output n, or sets it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [/table]0pt]STATELD：14 [/td] [td] Configures the way STATEV modifies the state set by HEVENT (the state modification occurs when this event is the highest-numbered event). 0 The value of STATEV is added to STATE. (The carry is discarded) 1 The value of STATEV is directly loaded into STATE. [/td] [td] 0 [/td] [/tr] [tr] [td] [/td] [td] STATEV:19:15 [/td] [td] The state value or state increment is determined by STATELD. If STATELD and STATEV are both 0, the STATE value does not change. [/td] [td] 0 [/td] [/tr] [tr] [td] [/td] [td] MATCHMEM：20 [/td] [td] If this position is 1, and COMBMODE is set with a match condition, the event will be triggered as long as the counting condition is greater than or equal to the match setting when counting up, and less than or equal to the counting condition when counting down. If this position is 0, the match event will only occur in the clock cycle that is equal to the match value. [/td] [td] - [/td] [/tr] [tr] [td] [/td] [td] DIRECTION：22：21 [/td] [td] The relationship between the occurrence of the event and the counting direction. Only valid in BIDIR＝1 mode. 0x0 The counting direction is irrelevant. The occurrence of this event is irrelevant to the counting direction. 0x1 Counting upwards. This event occurs only when counting up. 0x2 Counting down. This event occurs only when counting down. [/td] [td] - [/td] [/tr] [tr] [td] OUT[0:9]_SET [/td] [td] SET:15:0 [/td] [td] If position n is 1, event n sets output n, or clears it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [tr] [td] OUT[0:9]_CLR [/td] [td] CLR:15:0 [/td] [td] If position n is set, event n clears output n, or sets it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [/table]0pt]1 The value of STATEV is loaded directly into STATE. [/td] [td] 0 [/td] [/tr] [tr] [td] [/td] [td] STATEV:19:15 [/td] [td] The state value or state increment is determined by STATELD. If STATELD and STATEV are both 0, the value of STATE does not change. [/td] [td] 0 [/td] [/tr] [tr] [td] [/td] [td] MATCHMEM：20 [/td] [td] If this position is 1, and COMBMODE is set with a match condition, the event will be triggered as long as the counting condition is greater than or equal to the match setting when counting up, and less than or equal to the counting condition when counting down. If this position is 0, the match event will only occur in the clock cycle that is equal to the match value. [/td] [td] - [/td] [/tr] [tr] [td] [/td] [td] DIRECTION：22：21 [/td] [td] The relationship between the occurrence of the event and the counting direction. Only valid in BIDIR＝1 mode. 0x0 The counting direction is irrelevant. The occurrence of this event is irrelevant to the counting direction. 0x1 Counting upwards. This event occurs only when counting up. 0x2 Counting down. This event occurs only when counting down. [/td] [td] - [/td] [/tr] [tr] [td] OUT[0:9]_SET [/td] [td] SET:15:0 [/td] [td] If position n is 1, event n sets output n, or clears it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [tr] [td] OUT[0:9]_CLR [/td] [td] CLR:15:0 [/td] [td] If position n is set, event n clears output n, or sets it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [/table]0pt]1 The value of STATEV is loaded directly into STATE. [/td] [td] 0 [/td] [/tr] [tr] [td] [/td] [td] STATEV:19:15 [/td] [td] The state value or state increment is determined by STATELD. If STATELD and STATEV are both 0, the value of STATE does not change. [/td] [td] 0 [/td] [/tr] [tr] [td] [/td] [td] MATCHMEM：20 [/td] [td] If this position is 1, and COMBMODE is set with a match condition, the event will be triggered as long as the counting condition is greater than or equal to the match setting when counting up, and less than or equal to the counting condition when counting down. If this position is 0, the match event will only occur in the clock cycle that is equal to the match value. [/td] [td] - [/td] [/tr] [tr] [td] [/td] [td] DIRECTION：22：21 [/td] [td] The relationship between the occurrence of the event and the counting direction. Only valid in BIDIR＝1 mode. 0x0 The counting direction is irrelevant. The occurrence of this event is irrelevant to the counting direction. 0x1 Counting upwards. This event occurs only when counting up. 0x2 Counting down. This event occurs only when counting down. [/td] [td] - [/td] [/tr] [tr] [td] OUT[0:9]_SET [/td] [td] SET:15:0 [/td] [td] If position n is 1, event n sets output n, or clears it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [tr] [td] OUT[0:9]_CLR [/td] [td] CLR:15:0 [/td] [td] If position n is set, event n clears output n, or sets it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [/table]0pt]If this position is 1, and COMBMODE is set with match conditions, the event will be triggered as long as the counting conditions are greater than or equal to the match setting when counting upwards, and less than or equal to the match setting when counting downwards. If this position is 0, the match event will only occur in the clock cycle that is equal to the match value. [/td] [td] - [/td] [/tr] [tr] [td] [/td] [td] DIRECTION：22：21 [/td] [td] The relationship between the occurrence of the event and the counting direction. Only valid in BIDIR＝1 mode. 0x0 Count direction is irrelevant. This event occurs regardless of the counting direction. 0x1 Count up. This event occurs only when counting up. 0x2 Count down. This event occurs only when counting down. [/td] [td] - [/td] [/tr] [tr] [td] OUT[0:9]_SET [/td] [td] SET:15:0 [/td] [td] If position n is 1, event n sets output n, or clears it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [tr] [td] OUT[0:9]_CLR [/td] [td] CLR:15:0 [/td] [td] If position n is set, event n clears output n, or sets it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [/table]0pt]If this position is 1, and COMBMODE is set with match conditions, the event will be triggered as long as the counting conditions are greater than or equal to the match setting when counting upwards, and less than or equal to the match setting when counting downwards. If this position is 0, the match event will only occur in the clock cycle that is equal to the match value. [/td] [td] - [/td] [/tr] [tr] [td] [/td] [td] DIRECTION：22：21 [/td] [td] The relationship between the occurrence of the event and the counting direction. Only valid in BIDIR＝1 mode. 0x0 Count direction is irrelevant. This event occurs regardless of the counting direction. 0x1 Count up. This event occurs only when counting up. 0x2 Count down. This event occurs only when counting down. [/td] [td] - [/td] [/tr] [tr] [td] OUT[0:9]_SET [/td] [td] SET:15:0 [/td] [td] If position n is 1, event n sets output n, or clears it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [tr] [td] OUT[0:9]_CLR [/td] [td] CLR:15:0 [/td] [td] If position n is set, event n clears output n, or sets it according to the configuration of SETCLRn =0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [/table]9]_CLR [/td] [td] CLR:15:0 [/td] [td] If bit n is set, event n clears output n, or sets it according to the configuration of SETCLRn = 0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [/table]9]_CLR [/td] [td] CLR:15:0 [/td] [td] If bit n is set, event n clears output n, or sets it according to the configuration of SETCLRn = 0x1 or 0x2. event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15 [/td] [td] [/td] [/tr] [/table]
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