DSP Challenges Instruction Cycles

1134974591

DSP Challenges Instruction Cycles [Copy link]

     Dear experts, when single-step debugging the C6701 DSP program under CCS, disassembled code will appear. Most of the time, when encountering B instruction in the disassembled code, it does not jump immediately, and there are 5 delay gaps (this is also written in the official documentation). However, some B instructions have 0 or 1 delay gaps. Why does this happen? Is it related to the cache or what? Please tell me, thank you. The following is the disassembly code style:

0000384 05bce2f6 || STW.D2T2 B11,*+B15[7]

00000388 06254075 STW.D1T1 A12,*-A9[10]

0000038c 053cc2f6 || STW.D2T2 B10,*+B15[6]

00000390 009058d9 CMPGT.L1X 2,B4,A1

00000394 078000a9 || MVK.S1 0x0001,A15

00000398 05100941 || MV.D1 A4,A10

0000039c 0610005a || MV.L2 B4,B12

000003a0 960000f9 [!A1] ZERO.L1 A12

000003a4 80003d10 || [ A1] B.S1 0x000588

000003a8 06901058 MV.L1X B4,A13

000003ac 0134105a MV.L2X A13,B2

000003b0 02101058MV.L1X B4,A4

000003b4 06b42da0 SHR.S1 A13,0x1,A13

000003b8 00b40ad9 CMPLT.L1 0,A13,A1

000003bc 00000000 || NOP

000003c0 85b4105b [ A1] MV.L2X A13,B11

000003c4 90003010 || [!A1] B.S1 0x000540

000003c8 870000f8 [ A1] ZERO.L1 A14

000003cc 85b44ca0 [ A1] SHL.S1 A13,0x2,A11

000003d0 00918af8 CMPLT.L1 A12,A4,A1

电子微创意

Is it related to parallel operation?

1134974591

Electronic Micro Creativity published on 2015-12-11 21:50 Is it related to parallel operation?

It seems that parallel instructions cannot be regarded as one instruction. When looping, the delay interval of instruction B is sometimes not 5 cycles.