SUMMIT
MICROELECTRONICS, Inc.
S9408
Serial Input, Quad 8-Bit Nonvolatile DACPOT™
FEATURES
• Four 8-Bit DACS
– Differential Non-linearity - ±0.5LSB max
– Integral Non-Linearity - ±1LSB max
• Each DAC has Independent Reference Inputs
– Output Buffer Amplifiers Swing Rail-to-Rail
– Ground to V
DD
Reference Input Range
• Each DAC’s Digital Input Data Maintained in
Nonvolatile EEPROM
• Power-On Reset Reloads Registers with
Nonvolatile Data
• Simple Serial Interface for Reading and Writing
DAC values, SPI™ and QSPI™ compatible.
• Fully operational from 2.7V to 5.5V
• Low Power: <1mW @ 2.7V
OVERVIEW
The S9408 DACPOT™ is a serial input, voltage output,
quad 8-bit digital to analog converter. The S9408 oper-
ates from a single +2.7V to +5.5V supply. Internal preci-
sion buffers swing rail-to-rail and the reference input
range includes both ground and the positive supply.
The S9408 integrates four 8-bit DACs and their associ-
ated circuits which include an enhanced unity-gain opera-
tional amplifier output, an 8-bit data latch, an 8-bit non-
volatile register, and an industry-standard serial interface
for reading and writing data to the DACs’ data latches and
registers. The DACs are independently programmable
and each has its own electrically isolated Vreference
inputs.
FUNCTIONAL BLOCK DIAGRAM
Memory Control
8-Bit E2PROM
DAC SECTION 0
2
VREFH0
VDD
3
Serial
Data In
8-Bit Data Register
8-Bit DAC
AMP
18
VOUT0
RDY/BSY#
4
Programming
Memory
Controller
11
Serial Data Out
1
DAC SECTION 1
17
12
VREFL0
VREFH1
VOUT1
VREFL1
CS#
DI
CLK
6
7
5
Control
Logic
20
00/REG#
9
DAC SECTION 2
GND
10
16
13
VREFH2
VOUT2
VREFL2
19
DAC SECTION 3
15
14
8
2015 T BD 2.0
VREFH3
VOUT3
VREFL3
DO
© SUMMIT MICROELECTRONICS, Inc. 2000 • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
Characteristics subject to change without notice
2015 2.2 8/2/00
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S9408
PINOUT and SIGNAL DEFINITION
Pin
Name
Function
Vreference High:
V
REFL
< V
REFH
- V
DD
Power Supply Voltage
20-Pin PDIP
or 20-Pin SOIC
1, 2
V
REFH
20, 19
3
V
DD
VREFH1
VREFH0
VDD
RDY/BSY#
CLK
CS#
DI
DO
00/REG#
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VREFH2
VREFH3
VOUT0
VOUT1
VOUT2
VOUT3
VREFL3
VREFL2
VREFL1
VREFL0
2015 T PCon 2.0
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RDY/BSY# Ready/Busy: open drain output
indicating status of nonvolatile
write operations
CLK
CS#
Clock Input Pin: used for serial
data communication
Chip Select: When high deselects
the device and places it in a low
power mode
Data Input: serial data input pin
Data Output: serial data output pin
Power On Recall Option Input
Power Supply Ground
Vreference Low:
V
REFH
> V
REFL
• GND
DAC Output: buffered D to A
converter output
5
6
7
8
9
10
11, 12
13, 14
15, 16
17, 18
DI
DO
00/REG#
GND
V
REFL
V
OUT
The analog outputs of the S9408 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256
th
of the voltage differential between V
REFH
and
V
REFL
of the respective DAC. Once programmed these
settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition, each output can be adjusted an unlim-
ited number of times without altering the value stored in
the nonvolatile memory.
DEVICE OPERATION
Analog Section
The S9804 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
Reference inputs
The voltage differential between the V
REFL
and V
REFH
inputs sets the full-scale output voltage for its respective
DAC. V
REFL
must be equal to or greater than ground
(positive voltage). V
REFH
must be greater (more positive)
than V
REFL
and less than or equal to V
DD
.
Output Buffer Amplifiers
The voltage outputs are precision unity-gain followers that
slew up to 1V/µs. The outputs can swing from V
REFL
to
V
REFH
. With a 0V to 5V output transition the amplifier
outputs typically settle to 1LSB in 40µs.
DIGITAL INTERFACE
The S9408 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (CS#), Data In
(DI) and Data Out (DO). Data is clocked into the device on
the clock’s rising edge and out of the device on the clock’s
falling edge. Data is shifted in and out MSB first. DO only
becomes active after the device has been selected and
after a valid read command and address has been re-
ceived.
All data transfers are initiated after CS# goes low and a
logic ‘1’ is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.
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SUMMIT MICROELECTRONICS, Inc.
S9408
Start
1
1
1
1
C
1
0
0
1
1
C
0
0
1
0
1
A
1
A
A
A
A
A
0
A
A
A
A
Command
NV Write Enable
Write — Data In
Read — Data Out
Recall
selected data register. This read will not affect the contents
of the register or the output of the DAC. Refer to Figure 1
for an illustration of the sequence of bus conditions for a
read operation.
WRITE
Write operations are initiated by taking CS# low and
clocking in a start bit followed by the write command and
the address of the data register to be written. This action
is followed by the host clocking eight bits of data into the
register, MSB first. The output of the selected DAC will
change as the last bit is clocked into the device. At this
point the clock counter will reset the command register,
requiring a full sequence to be initiated in order to write to
the DAC again.
TABLE 1. COMMAND FORMAT
Internally there are four DACs and associated with each
are two registers. There is one data register that is used
by the DAC to hold the digital value it converts. There is
also one nonvolatile register that holds the default value
that can be recalled into the data register during power-
up or by executing the Recall command.
READ
Read operations are initiated by taking CS# low and
clocking in a start bit followed by the read command and
the address of the data register to be read. The next eight
clocks will output on the DO pin the contents of the
NOTE:
This write operation does not affect the
contents of the nonvolatile register. Therefore, the
nonvolatile register can contain the power-on default
settings (e.g. volume), and the write DAC command
can be used to make situational adjustments.
Refer to Figure 2 for an illustration of the sequence of bus
conditions for a write operation.
CS#
CLK
DI
S
T
A
R
T
C1
C0
A1
A0
DO
Hi Z
D7
D6
D5
D4
D3
D2
D1
D0
Hi Z
(Pulled up to V
DD
)
RDY/BSY#
FIGURE 1. READ SEQUENCE
2015 T fig01 2.0
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SUMMIT MICROELECTRONICS, Inc.
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S9408
CS#
CLK
DI
S
T
A
R
T
C1
C0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DO
Hi Z
(Pulled up to V
DD
)
RDY/BSY#
VOUT
2015 T fig02 2.0
FIGURE 2. WRITE SEQUENCE
Rising Edge Sets
NV Write Enable Latch
Rising Edge Starts
NV Write
CS#
CLK
DI
C1
C0
A1
D0
C1
C0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
NV Write Enable
Latch is Reset
Address and Data
are Don’t Care
RDY/BSY#
2015 T fig03 2.0
FIGURE 3. NONVOLATILE WRITE SEQUENCE
NONVOLATILE WRITE
A nonvolatile write is a two step operation: it is initiated by
taking CS# low and clocking in a start bit followed by the
NV Enable command. At this point the host can take CS#
back high or continue clocking in data. This data is don’t
care and will be ignored by the S9408. If any command
other than write follows NV enable the NV latch will be
cleared.
Next, the host takes CS# low again and issues a write
command and address and then clocks in the eight data
bits to be programmed. The host will then bring CS# HIGH
and the data will be latched into the data register and a
nonvolatile write operation will commence.
The status of the nonvolatile write can be monitored on the
RDY/BSY# pin. A logic low indicates the write is still in
progress and the S9408 will not be accessible to the host;
a logic high indicates the write has completed and the
S9408 is ready for the next command. Refer to Figure 3
for an illustration of the sequence of bus conditions for a
nonvolatile write operation.
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SUMMIT MICROELECTRONICS, Inc.
S9408
RECALL COMMAND
The recall command will retrieve data from the selected
nonvolatile register and write it into the data register of the
associated DAC. This operation is initiated by taking CS#
low and clocking in a start bit followed by the recall
command and the address of the nonvolatile register to be
recalled. The eight bits of data are don’t care, so CS# can
be taken high any time after the address bits are clocked
in. Refer to Figure 4 for an illustration of the sequence of
bus conditions for a Recall operation.
Power-on recall
Whenever the S9408 is powered on the DAC output
values will be returned to the selected default setting. The
default setting can be the nonvolatile register contents or
all zeroes. The state of the 00/REG# pin will determine
which operation will be performed. If it is tied to ground (or
left floating) the nonvolatile register contents will be re-
called. Conversely, if it is tied to V
DD
the S9408 will recall
zeroes.
CS#
CLK
DI
S
T
A
R
T
C1
C0
A1
A0
V
OUT
2015 T fig04 2.0
FIGURE 4. RECALL COMMAND SEQUENCE
2015 2.2 8/2/00
SUMMIT MICROELECTRONICS, Inc.
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