3-Channel Digital Potentiometer with
Nonvolatile Memory
AD5255
FEATURES
3 channels:
Dual 512-position
Single 128-position
25 kΩ or 250 kΩ full-scale resistance
Low temperature coefficient:
Potentiometer divider 15 ppm/°C
Rheostat mode 35 ppm/°C
Nonvolatile memory retains wiper settings
Permanent memory write protection
Linear increment/decrement
±6 dB increment/decrement
I
2
C-compatible serial interface
2.7 V to 5.5 V single-supply operation
±2.25 V to ±2.75 V dual-supply operation
Power-on reset time
256 bytes general-purpose user EEPROM
11 bytes RDAC user EEPROM
GBIC and SFP compliant EEPROM
100-year typical data retention at T
A
= 55°C
V
DD
V
SS
GND
SCL
SDA
A0_RDAC
A1_RDAC
A0_E
A1_E
COMMAND
DECODE
LOGIC
POWER-ON
RESET
ADDRESS
DECODE
LOGIC
DECODE
LOGIC
I
2
C
SERIAL
INTERFACE
FUNCTIONAL BLOCK DIAGRAM
RDAC0
REGISTER
256 BYTES
USER
EEPROM
32 BYTES
RDAC
EEPROM
DATA
CONTROL
RDAC0
A0
W0
9 BIT
RDAC1
B0
RDAC1
REGISTER
A1
W1
9 BIT
RDAC2
B1
RDAC2
REGISTER
A2
W2
RS
7 BIT
B2
04555-0-001
WP
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement
RGB LED backlight control
White LED brightness adjustment
Programmable gain and offset control
Programmable filters
GENERAL DESCRIPTION
The AD5255 provides dual 512-position and a single
128-position digitally controlled variable resistors
1
(VR) in a
TSSOP package. This device performs the same electronic
adjustment function as a potentiometer, trimmer, or variable
resistor. Each VR offers a completely programmable value of
resistance between the A terminal and the wiper or the B
terminal and the wiper. The fixed A-to-B terminal resistance of
25 kΩ or 250 kΩ has a 1% channel-to-channel matching
tolerance and a nominal temperature coefficient of 35 ppm/°C.
Wiper position programming, EEPROM
2
reading, and EEPROM
writing is conducted via the standard 2-wire I
2
C interface. Pre-
vious/default wiper position settings can be stored in memory,
and refreshed upon system power-up.
Additional features of the AD5255 include preprogrammed
linear and logarithmic increment/decrement wiper changing.
The actual resistor tolerances are stored in EEPROM so that the
actual end-to-end resistance is known, which is valuable for
calibration in precision applications.
The AD5255 is available in a 24-lead TSSOP package. All parts
are guaranteed to operate over the extended industrial tempera-
ture range of −40°C to +85°C.
1
The terms programmable resistor, variable resistor, RDAC, and digital
potentiometer are used interchangeably.
2
The terms nonvolatile memory, EEMEM, and EEPROM are used
interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5255
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3
Electrical Characteristics ................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Interface Descriptions .................................................................... 10
I
2
C Interface ................................................................................ 10
EEPROM Interface..................................................................... 11
RDAC I
2
C Interface.................................................................... 12
Theory of Operation ...................................................................... 15
Linear Increment and Decrement Commands ...................... 15
Logarithmic Taper Mode Adjustment (±6 dB/step) .............. 15
Using Additional Internal Nonvolatile EEPROM .................. 16
Digital Input/Output Configuration........................................ 16
Multiple Devices on One Bus ................................................... 16
Level Shift for Bidirectional Communication ........................ 16
Terminal Voltage Operation Range ......................................... 16
Power-Up Sequence ................................................................... 17
Layout and Power Supply Biasing ............................................ 17
RDAC Structure.......................................................................... 17
Calculating the Programmable Resistance ............................. 17
Programming the Potentiometer Divider............................... 18
Applications..................................................................................... 19
Laser Diode Driver (LDD) Calibration................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5255
ELECTRICAL CHARACTERISTICS
Single supply: V
DD
= 2.7 V to 5.5 V and −40°C < T
A
< +85°C, unless otherwise noted.
Dual supply: V
DD
= +2.25 V or +2.75 V, V
SS
= −2.25 V or −2.75 V and −40°C < T
A
< +85°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS,
RHEOSTAT MODE
Resistor Differential Nonlinearity
2
Symbol
Conditions
Min
Typ
1
Max
Unit
R-DNL
Resistor Integral Nonlinearity
2
R-INL
R-INL
R-INL
Resistance Temperature Coefficent
Wiper Resistance
Channel Resistance Matching
Nominal Resistor Tolerance
DC CHARACTERISTICS,
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity
3
(∆R
WB
/R
WB
)/∆T × 10
6
R
WB
, 7-bit channel
R
WB
, 9-bit channels
R
WB
, 7-bit channel
R
WB
, 9-bit channels, V
DD
= 5.5 V
R
WB
, 9-bit channels, V
DD
= 2.7 V
V
DD
= 5 V, I
W
= 1 V/R
WB
V
DD
= 3 V, I
W
= 1 V/R
WB
Ch 1 and 2 R
WB
, Dx = 0x1FF
Dx = 0x3FF
−0.75
−2.5
−0.5
−2.0
−4.0
35
100
250
0.1
−15
+0.75
+2.5
+0.5
+2.0
+4.0
150
400
+15
LSB
LSB
LSB
LSB
LSB
ppm/°C
Ω
Ω
%
%
R
W
∆R
AB1
/∆R
AB2
∆R
AB
/R
AB
DNL
DNL
Integral Nonlinearity
3
INL
INL
(∆V
W
/V
W
)/∆T × 10
6
V
WFSE
V
WZSE
7-bit channel
9-bit channels
7-bit channel
9-bit channels
Code = half-scale
7-bit channel/9-bit channel,
code = full-scale
7-bit channel/9-bit channel,
code = zero-scale
−0.5
−2.0
−0.5
−2.0
15
−1/−2.75
0/0
+0.5
+2.0
+0.5
+2.0
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
Voltage Divider Temperature
Coefficent
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Terminal Voltage Range
4
Capacitance
5
Ax, Bx
Capacitance
5
Wx
Common-Mode Leakage Current
5, 8
DIGITAL INPUTS AND OUTPUTS
Input Logic High
0/0
1/2.0
V
A, B, W
C
A,B
C
W
I
CM
V
IH
V
SS
f = 1 kHz, measured to GND,
code = half-scale
f = 1 kHz, measured to GND,
code = half-scale
V
W
= V
DD
/2
V
DD
= 5 V, V
SS
= 0 V
V
DD
/V
SS
= +2.7 V/0 V or
V
DD
/V
SS
= ±2.5 V
V
DD
= 5 V, V
SS
= 0 V
V
DD
/V
SS
= +2.7 V/0 V or
V
DD
/V
SS
= ±2.5 V
R
PULL-UP
= 2.2 kΩ to V
DD
= 5 V,
V
SS
= 0 V
R
PULL-UP
= 2.2 kΩ to V
DD
= 5 V,
V
SS
= 0 V
WP = V
DD
A0 = GND
2.4
2.1
85
95
0.01
V
DD
V
pF
pF
1
µA
V
V
Input Logic Low
V
IL
0.8
0.6
4.9
0.4
9
3
V
V
V
V
µA
µA
Output Logic High (SDA)
Output Logic Low
WP Leakage Current
A0 Leakage Current
V
OH
V
OL
I
WP
I
A0
Rev. 0 | Page 3 of 20
AD5255
Parameter
Input Leakage Current (Excluding WP
and A0)
Input Capacitance
5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEMEM Data Storing Mode Current
EEMEM Data Restoring Mode Current
Power Dissipation
6
Power Supply Sensitivity
5
See the footnotes after Table 2.
Symbol
I
I
C
I
V
DD
V
DD
/V
SS
I
DD
I
SS
I
DD_STORE
I
DD_RESTORE
P
DISS
P
SS
Conditions
V
IN
= 0 V or V
DD
Min
Typ
1
Max
±1
Unit
µA
pF
5
V
SS
= 0 V
V
IH
= V
DD
or V
IL
= GND, V
SS
= 0 V
V
IH
= V
DD
or V
IL
= GND,
V
DD
= 2.5 V, V
SS
= −2.5 V
V
IH
= V
DD
or V
IL
= GND
V
IH
= V
DD
or V
IL
= GND
V
IH
= V
DD
= 5 V or V
IL
= GND
∆V
DD
= 5 V ± 10%
2.7
±2.25
5
−5
35
2.5
25
0.01
5.5
±2.75
15
−15
V
V
µA
µA
mA
mA
µW
%/%
75
0.025
t
8
SDA
t
1
t
8
t
9
t
6
SCL
t
2
P
S
t
4
t
3
t
5
S
t
7
P
t
10
Figure 2. I
2
C Timing Diagram
Rev. 0 | Page 4 of 20
04555-0-015
AD5255
ELECTRICAL CHARACTERISTICS
Single Supply: V
DD
= 3 V to 5.5 V and −40°C < T
A
< +85°C, unless otherwise noted.
Dual Supply: V
DD
= +2.25 V or +2.75 V , V
SS
= −2.25 V or −2.75 V and −40°C < T
A
< + 85°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC CHARACTERISTICS
5, 7
Bandwidth −3 dB
Total Harmonic Distortion
V
W
Settling Time
Symbol
BW
THD
W
t
S
Conditions
V
DD
/V
SS
= ±2.5 V, R
AB
= 25 kΩ/250 kΩ
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V,
V
W
= 0.50% error band,
code 0x000 to 0x100, R
AB
= 25 kΩ/250 kΩ
Min
Typ
1
125/12
0.05
4/36
Max
Unit
kHz
%
µs
Resistor Noise Spectral Density
Digital Crosstalk
e
N_WB
C
T
Analog Crosstalk
INTERFACE TIMING CHARACTERISTICS
(apply to all parts) (Notes
8, 9
)
SCL Clock Frequency
t
BUF
Bus Free Time between Stop and
Start
t
HD;STA
Hold Time (Repeated Start)
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Start Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
R
Rise Time of Both SDA and SCL
Signals
t
F
Fall Time of Both SDA and SCL
Signals
t
SU;STO
Setup Time for Stop Condition
EEMEM Data Storing Time
EEMEM Data Restoring Time at
Power-On
EEMEM Data Restoring Time on
Restore
Command or Reset Operation
EEMEM Data Rewritable Time
FLASH/EE MEMORY RELIABILITY
Endurance
10
Data Retention
11
C
AT
R
AB
= 25 kΩ/250 kΩ, T
A
= 25°C
V
A
= V
DD
, V
B
= 0 V, measure VW with
adjacent RDAC making full-scale
change
Signal input at A0 and measure output
at W1, f = 1 kHz
14/45
−80
nV√Hz
dB
−72
dB
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
EEMEM_STORE
t
EEMEM_RESTORE1
t
EEMEM_RESTORE2
After this period the first clock pulse is
generated
400
1.3
600
1.3
0.6
600
100
300
300
600
26
360
360
kHz
µs
ns
µs
µs
ns
ns
ns
ns
ns
ns
ms
µs
µs
50
900
t
EEMEM_REWRITE
540
100
55°C
100
µs
kcycles
years
1
2
Typical represent average readings at 25°C, V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
4
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
All dynamic characteristics use V
DD
= 5 V.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
See the timing diagram for location of measured values.
10
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at −40°C, +25°C, and +85°C, typical endurance at 25°C is 700,000 cycles.
11
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
derates with junction temperature.
Rev. 0 | Page 5 of 20
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