BX80526F667256E/SL3T2 datasheet, PDF

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BX80526F667256E/SL3T2: DescriptionRISC Microprocessor, 32-Bit, 667MHz, CMOS, PPGA370; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1010KB，94 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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BX80526F667256E/SL3T2 Overview

RISC Microprocessor, 32-Bit, 667MHz, CMOS, PPGA370

BX80526F667256E/SL3T2 Parametric

Parameter Name	Attribute value
Maker	Intel
package instruction	PGA, SPGA370,37X37
Reach Compliance Code	unknown
bit size	32
JESD-30 code	S-PPGA-P370
Number of terminals	370
Package body material	PLASTIC/EPOXY
encapsulated code	PGA
Encapsulate equivalent code	SPGA370,37X37
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.5,2,3.3 V
Certification status	Not Qualified
speed	667 MHz
Maximum slew rate	250 mA
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Pentium

III Processor for the PGA370

Socket at 500 MHz to 1.13 GHz

Datasheet

Revision 8

Product Features

Available in 1.13 GHz, 1B GHz, 933, 866,

800EB, 733, 667, 600EB, and 533EB MHz

for a 133 MHz system bus

Available in 1.10 GHz, 1 GHz, 900, 850,

800, 750, 700, 650, 600E, 550E, and 500E

MHz for a 100 MHz system bus

System bus frequency at 100 MHz and

133 MHz (“E” denotes support for

Advanced Transfer Cache and Advanced

system buffering; “B” denotes support for a

133 MHz system bus where both bus

frequencies are available for order per each

given core frequency; See Table 1 for a

summary of features for each line item.)

Available in versions that incorporate

256-KB Advanced Transfer Cache (on-die,

full speed Level 2 (L2) cache with Error

Correcting Code (ECC))

Dual Independent Bus (DIB) architecture:

Separate dedicated external System Bus and

dedicated internal high-speed cache bus

Internet Streaming SIMD Extensions for

enhanced video, sound and 3D performance

Binary compatible with applications running

on previous members of the Intel

microprocessor line

Dynamic execution micro architecture

Intel Processor Serial Number

Power Management capabilities

— System Management mode

— Multiple low-power states

Optimized for 32-bit applications running on

advanced 32-bit operating systems

Flip Chip Pin Grid Array (FC-PGA/FC-PGA2)

packaging technology; FC-PGA/FC-PGA2

processors deliver high performance with

improved handling protection and socketability

Integrated high performance 16-KB instruction

and 16-KB data, nonblocking, level one cache

256-KB Integrated Full Speed level two cache

allows for low latency on read/store operations

Double Quad Word Wide (256 bit) cache data

bus provides extremely high throughput on

read/store operations.

8-way cache associativity provides improved

cache hit rate on reads/store operations.

Error-correcting code for System Bus data

Enables systems which are scaleable for up to

two processors

The Pentium

III processor is designed for high-performance desktops and for workstations and

servers. It is binary compatible with previous Intel Architecture processors. The Pentium III processor

provides great performance for applications running on advanced operating systems such as Windows*

98, Windows NT and UNIX*. This is achieved by integrating the best attributes of Intel processors—

the dynamic execution, Dual Independent Bus architecture plus Intel MMX™ technology and Internet

Streaming SIMD Extentions— bringing a new level of performance for systems buyers. The Pentium

III processor is scaleable to two processors in a multiprocessor system and extends the power of the

Pentium

II processor with performance headroom for business media, communication and internet

capabilities. Systems based on Pentium III processors also include the latest features to simplify system

management and lower the cost of ownership for large and small business environments. The Pentium

III processor offers great performance for today’s and tomorrow’s applications.

FC-PGA370 Package

June 2001

Document Number

245264-08

Pentium

III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz

Contents

1.0

Introduction

.................................................................................................................. 8

1.1

Terminology........................................................................................................... 9

1.1.1 Package and Processor Terminology ...................................................... 9

1.1.2 Processor Naming Convention...............................................................10

Related Documents.............................................................................................11

Processor System Bus and V

REF

........................................................................13

Clock Control and Low Power States..................................................................14

2.2.1 Normal State—State 1 ...........................................................................15

2.2.2 AutoHALT Powerdown State—State 2...................................................15

2.2.3 Stop-Grant State—State 3 .....................................................................16

2.2.4 HALT/Grant Snoop State—State 4 ........................................................16

2.2.5 Sleep State—State 5..............................................................................16

2.2.6 Deep Sleep State—State 6 ....................................................................17

2.2.7 Clock Control..........................................................................................17

Power and Ground Pins ......................................................................................17

2.3.1 Phase Lock Loop (PLL) Power...............................................................18

Decoupling Guidelines .......................................................................................19

2.4.1 Processor VCC

CORE

and AGTL+ (AGTL) Decoupling ...........................19

Processor System Bus Clock and Processor Clocking .......................................19

2.5.1 Mixing Processors of Different Frequencies...........................................20

Voltage Identification ...........................................................................................20

Processor System Bus Unused Pins...................................................................22

Processor System Bus Signal Groups ................................................................22

2.8.1 Asynchronous vs. Synchronous for System Bus Signals .......................24

2.8.2 System Bus Frequency Select Signals (BSEL[1:0]) ...............................25

Maximum Ratings................................................................................................26

Processor DC Specifications...............................................................................27

2.10.1 ICC Slew Rate Specifications.................................................................33

AGTL / AGTL+ System Bus Specifications .........................................................36

System Bus AC Specifications ............................................................................37

2.12.1 I/O Buffer Model .....................................................................................37

BCLK/BCLK# and PICCLK Signal Quality Specifications and Measurement

Guidelines ...........................................................................................................46

AGTL+ / AGTL Signal Quality Specifications and Measurement Guidelines ......47

AGTL+ Signal Quality Specifications and Measurement Guidelines ..................48

3.3.1 Overshoot/Undershoot Guidelines .........................................................48

3.3.2 Overshoot/Undershoot Magnitude .........................................................49

3.3.3 Overshoot/Undershoot Pulse Duration...................................................49

3.3.4 Activity Factor .........................................................................................49

3.3.5 Reading Overshoot/Undershoot Specification Tables............................50

3.3.6 Determining if a System Meets the Overshoot/Undershoot

Specifications .........................................................................................51

Non-AGTL+ (Non-AGTL) Signal Quality Specifications and Measurement

1.2

2.0

Electrical Specifications

........................................................................................13

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

3.0

Signal Quality Specifications

..............................................................................46

3.1

3.2

3.3

3.4

Datasheet

Pentium

III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz

Guidelines ........................................................................................................... 54

3.4.1 Overshoot/Undershoot Guidelines ......................................................... 54

3.4.2 Ringback Specification........................................................................... 55

3.4.3 Settling Limit Guideline .......................................................................... 55

4.0

Thermal Specifications and Design Considerations

................................. 56

4.1

4.2

4.3

Thermal Specifications........................................................................................ 56

Processor Die Area ............................................................................................. 57

Thermal Diode..................................................................................................... 58

FC-PGA Mechanical Specifications .................................................................... 60

5.1.1 FC-PGA2 Mechanical Specifications ..................................................... 63

Processor Markings ............................................................................................ 65

5.2.1 Processor Markings for FC-PGA2.......................................................... 65

Recommended Mechanical Keep-Out Zones ..................................................... 66

Processor Signal Listing...................................................................................... 67

Mechanical Specifications for the Boxed Intel

Pentium

III Processor.............. 80

6.1.1 Boxed Processor Thermal Cooling Solution Dimensions....................... 80

6.1.2 Boxed Processor Heatsink Weight......................................................... 82

6.1.3 Boxed Processor Thermal Cooling Solution Clip ................................... 82

Thermal Specifications........................................................................................ 82

6.2.1 Boxed Processor Cooling Requirements ............................................... 82

Electrical Requirements for the Boxed Intel

Pentium

III Processor................. 83

6.3.1 Fan Heatsink Power Supply ................................................................... 83

Alphabetical Signals Reference .......................................................................... 85

Signal Summaries ............................................................................................... 92

5.0

Mechanical Specifications

.................................................................................. 60

5.1

5.2

5.3

5.4

6.0

Boxed Processor Specifications

....................................................................... 80

6.1

6.2

6.3

7.0

Processor Signal Description

............................................................................. 85

7.1

7.2

Datasheet

Pentium

III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz

Figures

Second Level (L2) Cache Implementation ........................................................... 8

AGTL+/AGTL Bus Topology in a Uniprocessor Configuration ............................14

AGTL+/AGTL Bus Topology in a Dual-Processor Configuration ........................14

Stop Clock State Machine ...................................................................................15

Processor Vcc

CMOS

Package Routing ................................................................18

Differential Clocking Example .............................................................................20

BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design .........25

Slew Rate (23A Load Step).................................................................................33

Generic Clock Waveform ....................................................................................41

BCLK, PICCLK, and TCK Generic Clock Waveform...........................................42

System Bus Valid Delay Timings ........................................................................42

System Bus Setup and Hold Timings..................................................................43

System Bus Reset and Configuration Timings....................................................43

Platform Power-On Sequence Timings ...............................................................44

Power-On Reset and Configuration Timings.......................................................45

BCLK, PICCLK Generic Clock Waveform at the Processor Pins........................47

Low to High AGTL+ Receiver Ringback Tolerance.............................................48

Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform .......................53

Maximum Acceptable AGTL Overshoot/Undershoot Waveform .........................53

Non-AGTL+ (Non-AGTL) Overshoot/Undershoot, Settling Limit, and

Ringback 1 ..........................................................................................................54

Processor Functional Die Layout for FC-PGA.....................................................58

FC-PGA and FC-PGA2 Package Types .............................................................60

Package Dimensions...........................................................................................61

Package Dimensions for FC-PGA2.....................................................................63

FC-PGA2 Flatness Specification.........................................................................64

Top Side Processor Markings for FC-PGA (up to CPUID 0x686H) ....................65

Top Side Processor Markings for FC-PGA (for CPUID 0x68AH)).......................65

Top Side Processor Markings for FC-PGA2 .......................................................66

Volumetric Keep-Out for FC-PGA and FC-PGA2................................................66

Component Keep-Out .........................................................................................67

Intel

Pentium

III Processor Pinout ...................................................................68

Conceptual Boxed Intel

Pentium

III Processor for the PGA370 Socket ..........80

Dimensions of Mechanical Step Feature in Heatsink Base.................................81

Dimensions of Notches in Heatsink Base ...........................................................82

Thermal Airspace Requirement for all Boxed Intel

Pentium

III Processor Fan

Heatsinks in the PGA370 Socket ........................................................................83

Boxed Processor Fan Heatsink Power Cable Connector Description.................84

Motherboard Power Header Placement Relative to the Boxed

Intel

Pentium

III Processor ..............................................................................84

Datasheet

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