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CY6264-55SNXIT

Description
SRAM 64Kb 5V 55ns 8K x 8 SRAM
Categorystorage   
File Size1MB,16 Pages
ManufacturerCypress Semiconductor
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CY6264-55SNXIT Overview

SRAM 64Kb 5V 55ns 8K x 8 SRAM

CY6264-55SNXIT Parametric

Parameter NameAttribute value
Product CategorySRAM
ManufacturerCypress Semiconductor
RoHSDetails
Memory Size64 kbit
Organization8 k x 8
Access Time55 ns
Interface TypeParallel
Supply Voltage - Max5.5 V
Supply Voltage - Min4.5 V
Supply Current - Max200 mA
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package / CaseSOIC-28
PackagingCut Tape
PackagingMouseReel
PackagingReel
Data RateSDR
Memory TypeSDR
Moisture SensitiveYes
Number of Ports1
Operating Temperature Range- 40 C to + 85 C
Factory Pack Quantity1000
TypeAsynchronous
Unit Weight0.078125 oz
CY6264
8K × 8 Static RAM
8K × 8 Static RAM
Features
Functional Description
The CY6264 is a high-performance CMOS static RAM organized
as 8192 words by 8 bits. Easy memory expansion is provided by
an active LOW chip enable (CE
1
), an active HIGH chip enable
(CE
2
), and active LOW output enable (OE) and three-state
drivers. Both devices have an automatic power-down feature
(CE
1
), reducing the power consumption by over 70% when
deselected. The CY6264 is packaged in a 450-mil (300-mil body)
SOIC.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
1
and WE
inputs are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address pins
(A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH. A die coat is used to ensure alpha immunity.
For a complete list of related documentation, click
here.
Temperature ranges:
Commercial: 0 °C to 70 °C
Industrial: –40 °C to 85 °C
Automotive-A: –40 °C to 85 °C
High speed
55 ns
CMOS for optimum speed/power
Easy memory expansion with CE
1
, CE
2
and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
Available in Pb-free 28-pin SNC package
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-02367 Rev. *G
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised October 17, 2016

CY6264-55SNXIT Related Products

CY6264-55SNXIT CY6264-70SNXCT
Description SRAM 64Kb 5V 55ns 8K x 8 SRAM SRAM 64Kb 5V 70ns 8K x 8 SRAM
Product Category SRAM SRAM
Manufacturer Cypress Semiconductor Cypress Semiconductor
RoHS Details Details
Memory Size 64 kbit 64 kbit
Organization 8 k x 8 8 k x 8
Access Time 55 ns 70 ns
Interface Type Parallel Parallel
Supply Voltage - Max 5.5 V 5.5 V
Supply Voltage - Min 4.5 V 4.5 V
Supply Current - Max 200 mA 100 mA
Minimum Operating Temperature - 40 C 0 C
Maximum Operating Temperature + 85 C + 70 C
Mounting Style SMD/SMT SMD/SMT
Package / Case SOIC-28 SOIC-28
Packaging Reel Reel
Data Rate SDR SDR
Memory Type SDR SDR
Moisture Sensitive Yes Yes
Number of Ports 1 1
Operating Temperature Range - 40 C to + 85 C 0 C to + 70 C
Factory Pack Quantity 1000 1000
Type Asynchronous Asynchronous
Unit Weight 0.078125 oz 0.078125 oz

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