NB2304AC2DR2G datasheet, PDF - EEWORLD Datasheet

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NB2304AC2DR2G: DescriptionPhase Locked Loops - PLL 3.3V Quad Output Zero Delay Buffer; Categorylogic logic; File Size146KB，7 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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NB2304AC2DR2G Overview

Phase Locked Loops - PLL 3.3V Quad Output Zero Delay Buffer

NB2304AC2DR2G Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ON Semiconductor
Parts packaging code	SOIC
package instruction	SOP,
Contacts	8
Reach Compliance Code	compliant
series	2304
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e3
length	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	4
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.4 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
minfmax	133.3 MHz

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NB2304A

3.3 V Zero Delay

Clock Buffer

The NB2304A is a versatile, 3.3 V zero delay buffer designed to

distribute high-

-speed clocks in PC, workstation, datacom, telecom

and other high-

-performance applications. It is available in an 8 pin

package. The part has an on-

-chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback is required to be driven

to FBK pin, and can be obtained from one of the outputs. The

input- -output propagation delay is guaranteed to be less than

-to-

250 ps, and the output- -output skew is guaranteed to be less than

-to-

200 ps.

The NB2304A has two Banks of two outputs each. Multiple

NB2304A devices can accept the same input clock and distribute it. In

this case, the skew between the outputs of the two devices is

guaranteed to be less than 500 ps.

The NB2304A is available in two different configurations (Refer to

NB2304A Configurations Table). The NB2304AI1 is the base part,

where the output frequencies equal the reference if there is no counter

in the feedback path. The NB2304AI1H is the high-

-drive version of

the - and the rise and fall times on this device are much faster.

-1

The NB2304AI2 allows the user to obtain REF, 1/2 X and 2X

frequencies on each output Bank. The exact configuration and output

frequencies depend on which output drives the feedback pin.

Features

http://onsemi.com

MARKING

DIAGRAM*

SOIC-

-8

D SUFFIX

CASE 751

XXXX

ALYW

XXXX

= Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb--Free Package

*For additional marking information, refer to

Application Note AND8002/D.



Zero Input -- Output Propagation Delay, Adjustable by Capacitive



Load on FBK Input

Multiple Configurations - Refer to NB2304A Configurations Table

Input Frequency Range: 15 MHz to 133 MHz

Multiple Low-

-Skew Outputs

Output-

-Output Skew < 200 ps

Device-

-Device Skew < 500 ps

Two Banks of Four Outputs

Less than 200 ps Cycle- -Cycle Jitter (- -

-to-

-1, -1H, -

-5H)

Available in Space Saving, 8 pin 150 mil SOIC Package

3.3 V Operation

Advanced 0.35

CMOS Technology

Guaranteed Across Commercial and Industrial Temperature Ranges

These are Pb-

-Free Devices

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.



Semiconductor Components Industries, LLC, 2010

October, 2010 - Rev. 9

Publication Order Number:

NB2304A/D

NB2304AC2DR2G Related Products

	NB2304AC2DR2G	NB2304AC1HDG	NB2304AI2D
Description	Phase Locked Loops - PLL 3.3V Quad Output Zero Delay Buffer	Phase Locked Loops - PLL 3.3V Quad Output Zero Delay Buffer	Phase Locked Loops - PLL 3.3V Quad Output
Is it Rohs certified?	conform to	conform to	incompatible
Parts packaging code	SOIC	SOIC	SOIC
package instruction	SOP,	SOP,	SOP,
Contacts	8	8	8
Reach Compliance Code	compliant	compliant	not_compliant
series	2304	2304	2304
Input adjustment	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e3	e3	e0
length	4.9 mm	4.9 mm	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1	1	1
Number of functions	1	1	1
Number of terminals	8	8	8
Actual output times	4	4	4
Maximum operating temperature	70 °C	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	240
Certification status	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.4 ns	0.2 ns	0.4 ns
Maximum seat height	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin (Sn)	Tin (Sn)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	40	30
width	3.9 mm	3.9 mm	3.9 mm
minfmax	133.3 MHz	133.3 MHz	133.3 MHz
Maker	ON Semiconductor	ON Semiconductor	-

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