®
Intel
Data Sheet
Six-Interface SPI-4.2 Interconnect
FM1010
December, 2007 (Revision 2.0)
Intel
®
FM1010 Six-Interface SPI-4.2 Interconnect Data Sheet
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Intel
®
FM1010 Six-Interface SPI-4.2 Interconnect Data Sheet
Table of Contents
Product Highlights .......................................................................................... 6
Applications....................................................................................................6
FM1010 Features ............................................................................................6
Document Revision History.............................................................................7
Product Applicability.......................................................................................7
Other Related Documents and Tools ...............................................................8
1.0
General Description ............................................................................... 9
1.1
FM1010 Overview............................................................................ 9
1.2
FM1010 Application Example........................................................... 10
1.3
Definitions .................................................................................... 12
1.3.1 Terms Defined in the OIF SPI-4.2 Implementation Agreement .. 12
1.3.2 Other Relevant Terms ......................................................... 13
Theory of Operation ............................................................................. 14
2.1
Operating Modes ........................................................................... 14
2.1.1 Clear Mode ........................................................................ 15
2.1.2 Multi-Port Mode.................................................................. 16
2.1.3 Extended Multi-Port Mode .................................................... 17
2.2
Mixing Operating Modes ................................................................. 17
Functional Descriptions........................................................................ 19
3.1
Chip Reset and Configuration .......................................................... 21
3.1.1 Chip Reset Parameters ........................................................ 21
3.1.2 Reset and Configuration Procedure ....................................... 21
3.1.3 Mode-Independent Global Start-up Parameters ...................... 22
3.1.4 Mode-Independent SPI-4.2 Start-up Parameters..................... 22
3.1.5 Mode-Dependent Start-up Parameters................................... 23
3.2
Chip Operation .............................................................................. 26
3.2.1 Statistics ........................................................................... 26
3.2.2 Link/Port Reset Procedure.................................................... 26
3.2.3 Interrupt Processing ........................................................... 27
3.3
SPI-4.2 Interface........................................................................... 27
3.4
CPU Interface ............................................................................... 28
3.4.1 General Description ............................................................ 28
3.4.2 Register Read/Write Operations............................................ 28
3.4.3 CPU Interface Operation ...................................................... 29
3.4.4 Bus Error Condition Handling ............................................... 31
3.5
JTAG Interface .............................................................................. 31
3.6
Clocks.......................................................................................... 32
3.6.1 SPI-4.2 Receive and Transmit Data Path Clocks ...................... 32
3.6.2 CPU Interface Clock ............................................................ 32
3.6.3 JTAG Interface Clock........................................................... 32
Electrical Specifications ....................................................................... 33
4.1
Absolute Maximum Ratings ............................................................. 33
4.2
Recommended Operating Conditions ................................................ 33
4.3
AC Timing Specifications................................................................. 36
4.3.1 SPI-4 Interface .................................................................. 36
4.3.2 CPU Interface, General Timing Requirements ......................... 36
4.3.3 JTAG Interface ................................................................... 37
Register Definitions ............................................................................. 39
5.1
Memory Map................................................................................. 39
2.0
3.0
4.0
5.0
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Intel
®
FM1010 Six-Interface SPI-4.2 Interconnect Data Sheet
5.2
5.3
5.4
5.5
6.0
FM1010 Global and CPU Interface Register Definitions ........................41
SPI-4.2 Interface Register Descriptions .............................................43
5.3.1 RX_RESET .........................................................................43
5.3.2 RX_CAL_LM .......................................................................43
5.3.3 RX_SYNC ...........................................................................44
5.3.4 RX_DESKEW1.....................................................................44
5.3.5 RX_DESKEW2.....................................................................44
5.3.6 RX_DESKEW3.....................................................................45
5.3.7 RX_CALS ...........................................................................45
5.3.8 RX_FS ...............................................................................46
5.3.9 RX_OP_MODE ....................................................................46
5.3.10 RX_WATERMARK ................................................................46
5.3.11 RX_PORT2FIFO[0..31] .........................................................47
5.3.12 RX_PORT_VALID[0..7].........................................................47
5.3.13 RX_STATUS_OVERRIDE .......................................................48
5.3.14 RX_OS ..............................................................................49
5.3.15 RX_LINKCFG1[0..15]...........................................................49
5.3.16 RX_LINKCFG2[0..15]...........................................................50
5.3.17 RX_LINK_RESET .................................................................50
5.3.18 RX_PKTCNT .......................................................................51
5.3.19 RX_PKTERRCNT ..................................................................51
5.3.20 RX_DATACNT .....................................................................52
5.3.21 RX_ IP...............................................................................52
5.3.22 RX_IM ...............................................................................53
5.3.23 RX_DEBUG_STATUS............................................................53
5.3.24 TX_RESET..........................................................................55
5.3.25 TX_CAL_LM........................................................................55
5.3.26 TX_SYNC0 .........................................................................55
5.3.27 TX_SYNC1 .........................................................................56
5.3.28 TX_CORE_WATERMARK .......................................................56
5.3.29 TX_CALS ...........................................................................57
5.3.30 TX_FS ...............................................................................57
5.3.31 TX_OP_MODE.....................................................................58
5.3.32 TX_SERVICE_LIMIT.............................................................58
5.3.33 TX_MAX_BURST[0..15]........................................................59
5.3.34 TX_FIFO2PORT[0..15] .........................................................59
5.3.35 TX_FIFO_VALID ..................................................................59
5.3.36 TX_OS...............................................................................60
5.3.37 TX_LINKCFG[0..15].............................................................60
5.3.38 TX_PKTCNT........................................................................61
5.3.39 TX_PKTERRCNT ..................................................................61
5.3.40 TX_DATACNT .....................................................................61
5.3.41 TX_IP................................................................................62
5.3.42 TX_IM ...............................................................................62
5.3.43 TX_PLL_CTRL .....................................................................62
5.3.44 TX_PLL_STAT .....................................................................63
Watermark Recommendation...........................................................63
Memory Parity Errors......................................................................64
Signal, Ball, and Package Descriptions .................................................65
6.1
Package Overview..........................................................................65
6.2
Power Mapping ..............................................................................65
6.3
Interface Mapping ..........................................................................66
6.4
Signal Descriptions.........................................................................67
6.4.1 FM1010 Signals ..................................................................67
6.4.2 Power Supply Pins and Recommendations ..............................70
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Intel
®
FM1010 Six-Interface SPI-4.2 Interconnect Data Sheet
6.5
6.6
7.0
6.4.3 Ball Assignment ................................................................. 73
Package Dimensions .................................................................... 100
6.5.1 1232-Ball Version (FM1010-F1232)..................................... 100
6.5.2 1036-Ball Version (FM1010-F1036)..................................... 103
Recommended Heat Sink Vendors ................................................. 106
Document Revision Information ........................................................ 107
7.1
Nomenclature ............................................................................. 107
7.2
Rev 1.1 to 1.2 Changes ................................................................ 107
7.3
Rev 1.2 to 1.3 Changes ................................................................ 108
7.4
Rev 1.3 to 1.4 Changes ................................................................ 108
7.5
Rev 1.4 to 1.41 Changes .............................................................. 108
7.6
Rev 1.41 to 2.0 Changes .............................................................. 109
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