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PL130-58SC-R

Description
Clock Buffer Translator Buffer, Sine-Wave to CMOS Output
Categorylogic    logic   
File Size1MB,4 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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PL130-58SC-R Overview

Clock Buffer Translator Buffer, Sine-Wave to CMOS Output

PL130-58SC-R Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
package instructionSOP,
Reach Compliance Codecompliant
Other featuresIT ALSO OPERATES AT 3.3V
seriesPL130
JESD-30 codeR-PDSO-G8
JESD-609 codee3
length4.875 mm
Logic integrated circuit typeLOGIC CIRCUIT
Humidity sensitivity level1
Number of functions1
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Maximum seat height1.73 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width3.9 mm
PL130-58
High Speed Translator Buffer to PECL
FEATURES
Input clock frequency ≤266 MHz
JEDEC standard Differential LVPECL output
70mA typical power supply current
300ps Max. Rise/Fall time
740ps input propagation delay
LVCMOS and LVTTL Input compatible
Single 2.5V ±5% or 3.3V ±10% power supply
with V
EE
=0V
Available in 8 pin SOP Green/RoHS compliant
Package
PIN CONFIGURATION
(TOP VIEW)
DNC
REF-IN
OE
DNC
1
8
VCC
Q
QB
VEE
PL130-58
SOP-8L
2
3
4
7
6
5
DESCRIPTION
The PL130-58 is a low cost, high performance, high
speed, translator buffer that produces a pair of dif-
ferential LVPECL outputs from CMOS input.
Outputs are JEDEC standard LVPECL signals.
The device is targeted for Backplane buffering, data distri-
bution, Fibre Channel and many other applications.
BLOCK DIAGRAM
QB
Input
Q
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 8/25/11 Page 1

PL130-58SC-R Related Products

PL130-58SC-R PL130-58SC
Description Clock Buffer Translator Buffer, Sine-Wave to CMOS Output Clock Buffer Translator Buffer, Sine-Wave to CMOS Output
Is it Rohs certified? conform to conform to
Maker Microchip Microchip
package instruction SOP, SOP,
Reach Compliance Code compliant compliant
Other features IT ALSO OPERATES AT 3.3V IT ALSO OPERATES AT 3.3V
series PL130 PL130
JESD-30 code R-PDSO-G8 R-PDSO-G8
JESD-609 code e3 e3
length 4.875 mm 4.875 mm
Logic integrated circuit type LOGIC CIRCUIT LOGIC CIRCUIT
Humidity sensitivity level 1 1
Number of functions 1 1
Number of terminals 8 8
Maximum operating temperature 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE
Maximum seat height 1.73 mm 1.73 mm
Maximum supply voltage (Vsup) 2.625 V 2.625 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V
surface mount YES YES
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm
Terminal location DUAL DUAL
width 3.9 mm 3.9 mm

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