SPC564A74x, SPC564A80x
Errata sheet
SPC564A74x, SPC564A80x
devices errata JTAG_ID = 0x2AE02041
Introduction
This errata sheet describes all the functional and electrical problems known in the revision
3.0 of the SPC564A74x and SPC564A80x devices identified with the JTAG_ID =
0x2AE02041.
All the topics covered in this document refer to
RM0029 rev 7
and
SPC564A74B4,
SPC564A74L7, SPC564A80B4, SPC564A80L7 datasheet rev 8 (see
Appendix B:
Reference document).
Device identification:
•
Package device marking mask identifier: CA
•
JTAG_ID = 0x2AE02041
•
MIDR register:
– MAJOR_MASK: 2
– MINOR_MASK: 0
This errata sheet applies to SPC564A74x and SPC564A80x devices in accordance with
Table 1.
Table 1. Device summary
Part number
SPC564A74B4
SPC564A80B4
SPC564A74L7
SPC564A80L7
Package
PBGA324
LQFP176
July 2014
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1/20
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Contents
SPC564A74x, SPC564A80x
Contents
1
Functional problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
ERR001312: FLASH: MCR[DONE] bit may be set before high voltage
operation completes when executing a suspend sequence . . . . . . . . . . . . 5
ERR001397: Reaction Module: Register can set if RAER is asserted . . . . 5
ERR002382: FLASH: Flash Array Integrity Check . . . . . . . . . . . . . . . . . . . 6
ERR002740: ETPU2: Watchdog Status Register (WDSR) may fail to update
on channel timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ERR003221: PMC: SRAM standby power low voltage detect circuit is not
accurate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ERR003285: SIU: MCU ID register package information not reliable on the
calibration package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ERR003377: Pad Ring:Nexus pins may drive an unknown value
immediately after power up but before the 1st clock edge . . . . . . . . . . . . . 8
ERR003378: EQADC: Pull devices on differential pins may be enabled for a
short period of time during and just after POR . . . . . . . . . . . . . . . . . . . . . . 8
ERR003407: FlexCAN: CAN Transmitter Stall in case of no Remote Frame
in response to Tx packet with RTR=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ERR004480: eQADC: Differential conversions with 4x gain may halt
command processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ERR004532: REACM: OCDF flag is set during hold-off time . . . . . . . . . . 10
ERR005037: CRC: CRC-32 (Ethernet) and CRC-16 (CCITT) operation do
not match industry standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
ERR005086: eQADC: unexpected result may be pushed when Immediate
Conversion Command is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
ERR005640: ETPU2: Watchdog timeout may fail in busy length mode . . 12
ERR005642: ETPU2: Limitations of forced instructions executed via the
debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ERR006026: DSPI: Incorrect SPI Frame Generated in Combined Serial
Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ERR006726: NPC: MCKO clock may be gated one clock period early when
MCKO frequency is programmed as SYS_CLK/8.and gating is enabled . 14
ERR006967: eDMA: Possible misbehavior of a preempted channel when
using continuous link mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ERR007322: FlexCAN: Bus Off Interrupt bit is erroneously asserted when
soft reset is performed while FlexCAN is in Bus Off state . . . . . . . . . . . . 15
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Contents
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ERR007352: DSPI: reserved bits in slave CTAR are writable . . . . . . . . . 16
Appendix A Defect across silicon version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Appendix B Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of tables
SPC564A74x, SPC564A80x
List of tables
Table 1.
Table 2.
Table 3.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Defects across silicon version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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SPC564A74x, SPC564A80x
Functional problems
1
1.1
Functional problems
ERR001312: FLASH: MCR[DONE] bit may be set before high
voltage operation completes when executing a suspend
sequence
The program and erase sequence of the flash may be suspended to allow read and
program access to the flash core. An suspend operation is initiated by setting the Erase
Suspend (ESUS) bit or Program Suspend (PSUS) bit in the flash Module Configuration
Register (MCR). Setting a suspend bit causes the flash module to start the sequence which
places it in the suspended state. The user must then wait until the MCR[DONE] bit is set
before a read or program to the flash is initiated, as the high voltage operation needs to be
complete to avoid errors.
However, during normal read to the same partition, following a suspend sequence, (setting
MCR bit and waiting for MCR[DONE] bit to be set) can result in read fails that will return
multiple bit ECC errors. The error is due to the MCR[DONE] bit being set before the internal
high voltage operation is complete.
Description:
Workaround:
Because the MCR[DONE] flag can be set too soon, a delay needs to be inserted between
setting the MCR[ESUS] or MCR[PSUS] and reading the same flash partition. The minimum
duration of the delay should be 40us to guarantee correct operation. The Freescale flash
programming driver includes this workaround.
1.2
ERR001397: Reaction Module: Register can set if RAER is
asserted
A modulation can start if the RAER bit is asserted. The REACM_CHSR bit MODACT is
asserted.
Description:
Workaround:
Enable the RAER interrupt on the module initialization, asserting the REACM_CHCR bit
RAEREN. The interrupt service routine must disable the channel, setting the
REACM_CHCR field CHEN to zero.
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