• AN-202: An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change
•
AN-283: Sigma-Delta ADCs and DACs
•
AN-311: How to Reliably Protect CMOS Circuits Against
Power Supply Overvoltaging
•
AN-388: Using Sigma-Delta Converters-Part 1
•
AN-389: Using Sigma-Delta Converters-Part 2
•
AN-397: Electrically Induced Damage to Standard Linear
Integrated Circuits:
•
AN-553: Adjusting the Calibration Coefficients on the
AD771X Family of ADCs
•
AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma-
Delta ADC
•
AN-615: Peak-to-Peak Resolution Versus Effective
Resolution
Data Sheet
•
AD7714: CMOS, 3V/5V, 500 µA, 24-Bit Sigma-Delta, Signal
Conditioning ADC Data Sheet
User Guides
•
UG-761: Evaluation Board for the AD7714-3, 24-Bit Low
Power Sigma-Delta ADC
Technical Articles
•
Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
•
MS-2210: Designing Power Supplies for High Speed ADC
•
Part 1: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
•
Part 2: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
DESIGN RESOURCES
•
AD7714 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DISCUSSIONS
View all AD7714 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
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This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
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AD7714-5–SPECIFICATIONS
(AV
f
= 2.4576 MHz unless otherwise noted. All specifications T
CLK IN
= +5 V, DV
DD
= +3.3 V or +5 V, REF IN(+) = +2.5 V; REF IN(–) = AGND;
MIN
to T
MAX
unless otherwise noted.)
DD
Parameter
STATIC PERFORMANCE
No Missing Codes
A Versions
1
24
22
18
15
12
See Tables I to IV
±
0.0015
See Note 2
0.5
0.3
See Note 2
0.5
0.3
See Note 2
0.5
0.3
See Note 2
0.5
±
0.0015
1
0.6
90
100
100
150
150
AGND to AV
DD
AGND – 30 mV
AV
DD
+ 30 mV
AGND + 50 mV
AV
DD
– 1.5 V
1
7
0 to +V
REF
/GAIN
11
±
V
REF
/GAIN
GAIN
×
f
CLK IN
/64
f
CLK IN
/8
+2.5
f
CLK IN
/64
±
10
0.8
0.4
2.4
2.0
0.8
0.4
3.5
2.5
0.4
0.4
4.0
DV
DD
– 0.6 V
±
10
9
Binary
Offset Binary
Units
Bits min
Bits min
Bits min
Bits min
Bits min
% of FSR max
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
ppm of FSR/°C typ
% of FSR max
µV/°C
typ
µV/°C
typ
dB min
dB min
dB min
dB min
dB min
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
nom
Conditions/Comments
Guaranteed by Design. Bipolar Mode. For Filter Notches
≤
60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
≤
60 Hz
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Typically
±
0.0004%
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Specifications for AIN and REF IN Unless Noted
At DC. Typically 102 dB
For Filter Notches of 10
Hz,
25
Hz,
50 Hz,
±
0.02
For Filter Notches of 10
Hz,
30
Hz,
60 Hz,
±
0.02
For Filter Notches of 10
Hz,
25
Hz,
50 Hz,
±
0.02
For Filter Notches of 10
Hz,
30
Hz,
60 Hz,
±
0.02
AIN for BUFFER = 0 and REF IN
AIN for BUFFER = 0 and REF IN
BUFFER = 1. A Version
A Version
Unipolar Input Range (B/U Bit of Filter High Register = 1)
Bipolar Input Range (B/U Bit of Filter High Register = 0)
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
±
1% for Specified Performance. Functional with Lower V
REF
Output Noise
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift
3
Bipolar Zero Error
Bipolar Zero Drift
3
Positive Full-Scale Error
4
Full-Scale Drift
3, 5
Gain Error
6
Gain Drift
3, 7
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
3
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
Normal-Mode 50 Hz Rejection
8
Normal-Mode 60 Hz Rejection
8
Common-Mode 50 Hz Rejection
8
Common-Mode 60 Hz Rejection
8
Common-Mode Voltage Range
9
Absolute AIN/REF IN Voltage
9
Absolute/Common-Mode AIN Voltage
9
AIN Input Current
8
AIN Sampling Capacitance
8
AIN Differential Voltage Range
10
AIN Input Sampling Rate, f
S
REF IN(+) – REF IN(–) Voltage
REF IN Input Sampling Rate, f
S
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
Data Output Coding
×
f
NOTCH
×
f
NOTCH
×
f
NOTCH
×
f
NOTCH
V nom
µA
max
V max
V max
V min
V min
V max
V max
V min
V min
V max
V max
V min
V min
µA
max
pF typ
DV
DD
= +5 V
DV
DD
= +3.3 V
DV
DD
= +5 V
DV
DD
= +3.3 V
DV
DD
= +5 V
DV
DD
= +3.3 V
DV
DD
= +5 V
DV
DD
= +3.3 V
I
SINK
= 800
µA
Except for MCLK OUT.
12
DV
DD
= +5 V
I
SINK
= 100
µA
Except for MCLK OUT.
12
DV
DD
= +3.3 V
I
SOURCE
= 200
µA
Except for MCLK OUT.
12
DV
DD
= +5 V
I
SOURCE
= 100
µA
Except for MCLK OUT.
12
DV
DD
= +3.3 V
Unipolar Mode
Bipolar Mode
NOTES
1
Temperature range is as follows: A Versions: –40°C to +85°C.
2
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.
3
Recalibration at any temperature will remove these drift errors.
4
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
5
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
6
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for
bipolar ranges.
–2–
REV. C
AD7714
AD7714-3–SPECIFICATIONS
(AV
f
= 2.4576 MHz unless otherwise noted. All specifications T
CLK IN
= +3.3 V, DV
DD
= +3.3 V, REF IN(+) = +1.25 V; REF IN(–) = AGND;
MIN
to T
MAX
unless otherwise noted.)
DD
Parameter
STATIC PERFORMANCE
No Missing Codes
A Versions
24
22
18
15
12
See Tables I to IV
±
0.0015
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.2
±
0.003
1
0.6
90
100
100
150
150
AGND to AV
DD
AGND – 30 mV
AV
DD
+ 30 mV
AGND + 50 mV
AV
DD
– 1.5 V
1
7
0 to +V
REF
/GAIN
11
±
V
REF
/GAIN
GAIN
×
f
CLK IN
/64
f
CLK IN
/8
+1.25
f
CLK IN
/64
±
10
0.4
2.0
0.4
2.5
0.4
DV
DD
– 0.6
±
10
9
Binary
Offset Binary
Units
Bits min
Bits min
Bits min
Bits min
Bits min
% of FSR max
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
ppm of FSR/°C typ
% of FSR max
µV/°C
typ
µV/°C
typ
dB min
dB min
dB min
dB min
dB min
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
nom
Conditions/Comments
Guaranteed by Design. Bipolar Mode. For Filter Notches
≤
60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
≤
60 Hz
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Typically
±
0.0004%
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Specifications for AIN and REF IN Unless Noted
At DC. Typically 102 dB.
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
AIN for BUFFER = 0 and REF IN
AIN for BUFFER = 0 and REF IN
BUFFER = 1
Output Noise
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift
3
Bipolar Zero Error
Bipolar Zero Drift
3
Positive Full-Scale Error
4
Full-Scale Drift
3, 5
Gain Error
6
Gain Drift
3, 7
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
3
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
Normal-Mode 50 Hz Rejection
8
Normal-Mode 60 Hz Rejection
8
Common-Mode 50 Hz Rejection
8
Common-Mode 60 Hz Rejection
8
Common-Mode Voltage Range
9
Absolute AIN/REF IN Voltage
9
Absolute/Common-Mode AIN Voltage
9
AIN Input Current
8
AIN Sampling Capacitance
8
AIN Differential Voltage Range
10
AIN Input Sampling Rate, f
S
REF IN(+) – REF IN(–) Voltage
REF IN Input Sampling Rate, f
S
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
Data Output Coding
f
NOTCH
f
NOTCH
f
NOTCH
f
NOTCH
V nom
Unipolar Input Range (B/U Bit of Filter High Register = 1)
Bipolar Input Range (B/U Bit of Filter High Register = 0)
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
±
1% for Specified Performance. Part Functions with
Lower V
REF
µA
max
V max
V min
V max
V min
V max
V min
µA
max
pF typ
I
SINK
= 100
µA
Except for MCLK OUT
12
I
SOURCE
= 100
µA
Except for MCLK OUT
12
Unipolar Mode
Bipolar Mode
NOTES
7
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with
background calibration.
8
These numbers are guaranteed by design and/or characterization.
9
The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
10
The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII
for which inputs form differential pairs.
11
V
REF
= REF IN(+) – REF IN(–).
12
These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
13
Sample tested at +25°C to ensure compliance.
14
See Burnout Current section.
REV. C
–3–
AD7714–SPECIFICATIONS
(AV = + 3.3otherwiseV,noted.=All+3.3 V to +5 V, REF IN(+) =unless otherwise noted.)+2.5 V
V to +5 DV
+1.25 V (AD7714-3) or
(AD7714-5); REF IN(–) = AGND; MCLK IN = 1 MHz to 2.4576 MHz unless
specifications T to T
DD
DD
MIN
MAX
Parameter
TRANSDUCER BURNOUT
14
Current
Initial Tolerance
Drift
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
15
Negative Full-Scale Calibration Limit
15
Offset Calibration Limit
16
Input Span
16
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage (AD7714-3)
AV
DD
Voltage (AD7714-5)
DV
DD
Voltage
Power Supply Currents
AV
DD
Current
A Versions
1
±
10
0.1
(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
0.8
×
V
REF
/GAIN
(2.1
×
V
REF
)/GAIN
Units
µA
nom
% typ
%/°C typ
V max
V max
V max
V min
V max
Conditions/Comments
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
+3 to +3.6
+4.75 to +5.25
+3 to +5.25
V
V
V
For Specified Performance
For Specified Performance
For Specified Performance
AV
DD
= 3.3 V or 5 V. BST Bit of Filter High Register = 0
17
Typically 0.2 mA. BUFFER = 0 V. f
CLK IN
= 1 MHz or 2.4576 MHz
Typically 0.4 mA. BUFFER = DV
DD
. f
CLK IN
= 1 MHz or 2.4576 MHz
AV
DD
= 3.3 V or 5 V. BST Bit of Filter High Register = 1
17
Typically 0.3 mA. BUFFER = 0 V. f
CLK IN
= 2.4576 MHz
Typically 0.8 mA. BUFFER = DV
DD
. f
CLK IN
= 2.4576 MHz
Digital I/Ps = 0 V or DV
DD.
External MCLK IN
Typically 0.15 mA. DV
DD
= 3.3 V. f
CLK IN
= 1 MHz
Typically 0.3 mA. DV
DD
= 5 V. f
CLK IN
= 1 MHz
Typically 0.4 mA. DV
DD
= 3.3 V. f
CLK IN
= 2.4576 MHz
Typically 0.6 mA. DV
DD
= 5 V. f
CLK IN
= 2.4576 MHz
AV
DD
= DV
DD
= +3.3 V. Digital I/Ps = 0 V or DV
DD
. External MCLK IN
Typically 1.25 mW. BUFFER = 0 V. f
CLK IN
= 1 MHz. BST Bit = 0
Typically 1.8 mW. BUFFER = +3.3 V. f
CLK IN
= 1 MHz. BST Bit = 0
Typically 2 mW. BUFFER = 0 V. f
CLK IN
= 2.4576 MHz. BST Bit = 0
Typically 2.6 mW. BUFFER = +3.3 V. f
CLK IN
= 2.4576 MHz. BST Bit = 0
AV
DD
= DV
DD
= +5 V. Digital I/Ps = 0 V or DV
DD
. External MCLK IN
Typically 2.5 mW. BUFFER = 0 V. f
CLK IN
= 1 MHz. BST Bit = 0
Typically 3.5 mW. BUFFER = +5 V. f
CLK IN
= 1 MHz. BST Bit = 0
Typically 4 mW. BUFFER = 0 V. f
CLK IN
= 2.4576 MHz. BST Bit = 0
Typically 5 mW. BUFFER = +5 V. f
CLK IN
= 2.4576 MHz. BST Bit = 0
External MCLK IN = 0 V or DV
DD
. Typically 20
µA.
V
DD
= +5 V
External MCLK IN = 0 V or DV
DD
. Typically 5
µA.
V
DD
= +3.3 V
0.27
0.6
0.5
1.1
DV
DD
Current
18
0.23
0.4
0.5
0.8
See Note 20
1.65
2.75
2.55
3.65
Normal-Mode Power Dissipation
3.35
5
5.35
7
40
10
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
dB typ
mW max
mW max
mW max
mW max
mW max
mW max
mW max
mW max
µA
max
µA
max
Power Supply Rejection
19
Normal-Mode Power Dissipation
18
Standby (Power-Down) Current
21
Standby (Power-Down) Current
21
NOTES
15
After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.
16
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than AGND – 30 mV. The
offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
17
For higher gains (≥8) at f
CLK IN
= 2.4576 MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.
18
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD
current and power dissipation will vary depending on the crystal
or resonator type (see Clocking and Oscillator Circuit section).
19
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB
with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.
20
PSRR depends on gain. For Gain of 1 : 70 dB typ: For Gain of 2 : 75 dB typ; For Gain of 4 : 80 dB typ; For Gains of 8 to 128 : 85 dB typ.
21
If the external master clock continues to run in standby mode, the standby current increases to 150
µA
typical with 5 V supplies and 75
µA
typical with 3.3 V supplies. When
using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation
depends on the crystal or resonator type (see Standby Mode section).
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