EEWORLDEEWORLDEEWORLD

Part Number

Search

AGLP060V5-VQ176I

Description
FPGA - Field Programmable Gate Array IGLOO
CategoryProgrammable logic devices    Programmable logic   
File Size7MB,134 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

AGLP060V5-VQ176I Online Shopping

Suppliers Part Number Price MOQ In stock  
AGLP060V5-VQ176I - - View Buy Now

AGLP060V5-VQ176I Overview

FPGA - Field Programmable Gate Array IGLOO

AGLP060V5-VQ176I Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrosemi
package instruction20 X 20 MM, 1 MM HEIGHT, 0.4 MM PITCH, VQFP-176
Reach Compliance Codeunknown
maximum clock frequency250 MHz
JESD-30 codeS-PQFP-G176
length20 mm
Configurable number of logic blocks1584
Equivalent number of gates60000
Number of entries137
Number of logical units1584
Output times137
Number of terminals176
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1584 CLBS, 60000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeTFQFP
Encapsulate equivalent codeTQFP176,.87SQ,16
Package shapeSQUARE
Package formFLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage1.575 V
Minimum supply voltage1.425 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.4 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width20 mm
Revision 16
IGLOO PLUS Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low Power Active FPGA Operation
Flash*Freeze
Technology
Enables
Ultra-Low
Power
Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW State
per I/O in Flash*Freeze Mode
• Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode
Advanced I/O
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—4 Banks per Chip on All
IGLOO
®
PLUS Devices
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Selectable Schmitt Trigger Inputs
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Small-Footprint Packages across the IGLOO
PLUS Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Feature Rich
• 30 k to 125 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
Designed to Secure FPGA Contents
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Table 1 • IGLOO PLUS Product Family
IGLOO PLUS Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
Secure (AES) ISP
FlashROM Kbits
Integrated PLL in CCCs
1
VersaNet Globals
2
I/O Banks
Maximum User I/Os
Package Pins
CS
VQ
AGLP030
30,000
256
792
5
1
6
4
120
CS201, CS289
VQ128
AGLP060
60,000
512
1,584
10
18
4
Yes
1
1
18
4
157
CS201, CS289
VQ176
AGLP125
125,000
1,024
3,120
16
36
8
Yes
1
1
18
4
212
CS281, CS289
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
† The AGLP030 device does not support this feature.
December 2012
© 2012 Microsemi Corporation
I
Linux Common Clock Framework Summary
This post is a summary of Linux Common Clock Framework [url=https://bbs.eeworld.com.cn/thread-561667-1-1.html]Linux Common Clock Framework (1)[/url] [url=https://bbs.eeworld.com.cn/thread-562313-1-1.h...
okhxyyo Linux and Android
[Home smart lighting control and indoor environment monitoring system]--6. Bluetooth BLE host computer development 2
[i=s]This post was last edited by a media student on 2021-6-27 21:21[/i]After working hard for more than half a month, I found that it is still quite difficult to build an app from scratch. Share some...
传媒学子 onsemi and Avnet IoT Innovation Design Competition
Design of forehead thermometer based on SDI5229TS
Design of forehead thermometer based on SDI5229TS1.Development background of forehead thermometer The new coronavirus pneumonia epidemic is coming fiercely and has broken out on a large scale around t...
solidic Medical Electronics
A brief talk on thermal transfer technology
[size=10.5pt][size=10.5pt] Thermal transfer technology has been used in the production of fabric thermal transfer printing for a long time. With the rapid development of high technology, thermal trans...
mhsong0801 DIY/Open Source Hardware
What are the requirements for Press-fit on printed circuit boards?
What are the requirements for Press-fit on printed circuit boards?...
625745047 PCB Design
How did the heroes choose their career directions in the first place?
There are so many directions in electronics, and there is no good way to really experience what they are doing in school. I am already in my third year. I have just started my professional courses, in...
yuhc Talking about work

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 709  2851  1959  1480  1487  15  58  40  30  48 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号