Changes to Ordering Guide .......................................................... 14
4/2010—Revision 0: Initial Version
Rev. D | Page 2 of 16
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
ADuM3220/ADuM3221
All voltages are relative to their respective ground. 4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over T
J
= −40°C to +125°C. All typical specifications are at T
J
= 25°C, V
DD1
= 5 V, V
DD2
= 10 V. Switching
specifications are tested with CMOS signal levels.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current, Two Channels, Quiescent
Output Supply Current, Two Channels, Quiescent
Total Supply Current, Two Channels
1
DC to 1 MHz
V
DD1
Supply Current
V
DD2
Supply Current
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, V
DD2
Supply
ADuM3220A/ADuM3221A
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
ADuM3220B/ADuM3221B
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current
2
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width
3
Data Rate
4
Propagation Delay
5
Propagation Delay Skew
6
Channel-to-Channel Matching
7
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
Refresh Rate
1
Symbol
I
DDI(Q)
I
DDO(Q)
Min
Typ
1.2
4.7
Max
1.5
10
Unit
mA
mA
Test Conditions/Comments
I
DD1(Q)
I
DD2(Q)
I
IA
, I
IB
V
IH
V
IL
V
OAH
, V
OBH
V
OAL
, V
OBL
−10
0.7 × V
DD1
V
DD2
− 0.1
1.4
11
+0.01
1.7
17
+10
0.3 × V
DD1
V
DD2
0.0
0.15
mA
mA
µA
V
V
V
V
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0 V ≤ V
IA
, V
IB
≤ V
DD1
I
Ox
= −20 mA, V
Ix
= V
IxH
I
Ox
= +20 mA, V
Ix
= V
IxL
V
DD2UV+
V
DD2UV−
V
DD2UVH
V
DD2UV+
V
DD2UV−
V
DD2UVH
I
OA(SC)
, I
OB(SC)
R
OA
, R
OB
R
OA
, R
OB
PW
t
DLH
, t
DHL
t
DLH
, t
DHL
t
PSK
t
PSKCD
t
PSKCD
t
R
/t
F
t
R
/t
F
I
DDI(D)
I
DDO(D)
f
r
3.2
4.1
3.7
0.4
7.0
6.5
0.5
4.0
1.3
0.9
4.4
V
V
V
V
V
V
A
Ω
Ω
ns
MHz
ns
ns
ns
ns
ns
ns
ns
mA/Mbps
mA/Mbps
Mbps
7.5
6.0
2.0
0.3
0.3
50
35
36
3.0
3.0
V
DD2
= 10 V
V
DD2
= 10 V
V
DD2
= 10 V
C
L
= 2 nF, V
DD2
= 10 V
C
L
= 2 nF, V
DD2
= 10 V
C
L
= 2 nF, V
DD2
= 10 V; see Figure 20
C
L
= 2 nF, V
DD2
= 4.5 V; see Figure 20
C
L
= 2 nF, V
DD2
= 10 V; see Figure 20
C
L
= 2 nF, V
DD2
= 10 V; see Figure 20
C
L
= 2 nF, V
DD2
= 4.5 V; see Figure 20
C
L
= 2 nF, V
DD2
= 10 V; see Figure 20
C
L
= 2 nF, V
DD2
= 4.5 V; see Figure 20
V
DD2
= 10 V
V
DD2
= 10 V
45
50
1
1
20
22
0.05
1.5
1.2
14
14
1
60
68
12
5
7
25
28
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 9 and Figure 10 for total V
DD1
and V
DD2
supply currents as a function of frequency.
2
Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
3
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
5
t
DLH
propagation delay is measured from the time of the input rising logic high threshold, V
IH
, to the output rising 10% threshold of the V
Ox
signal. t
DHL
propagation
delay is measured from the input falling logic low threshold, V
IL
, to the output falling 90% threshold of the V
Ox
signal. See Figure 20 for waveforms of propagation
delay parameters.
6
t
PSK
is the magnitude of the worst-case difference in t
DLH
and/or t
DHL
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
7
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
Rev. D | Page 3 of 16
ADuM3220/ADuM3221
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
Data Sheet
All voltages are relative to their respective ground. 3.0 V ≤ V
DD1
≤ 3.6 V, 4.5 V ≤ V
DD2
≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over T
J
= −40°C to +125°C. All typical specifications are at T
J
= 25°C, V
DD1
= 3.3 V, V
DD2
= 10 V. Switching
specifications are tested with CMOS signal levels.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current, Two Channels, Quiescent
Output Supply Current, Two Channels,
Quiescent
Total Supply Current, Two Channels
1
DC to 1 MHz
V
DD1
Supply Current
V
DD2
Supply Current
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, V
DD2
Supply
ADuM3220A/ADuM3221A
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
ADuM3220B/ADuM3221B
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current
2
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width
3
Data Rate
4
Propagation Delay
5
Propagation Delay Skew
6
Channel-to-Channel Matching
7
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
Refresh Rate
1
Symbol
I
DDI(Q)
I
DDO(Q)
Min
Typ
0.7
4.7
Max
1.0
10
Unit
mA
mA
Test Conditions/Comments
I
DD1(Q)
I
DD2(Q)
I
IA
, I
IB
V
IH
V
IL
V
OAH
, V
OBH
V
OAL
, V
OBL
−10
0.7 × V
DD1
V
DD2
− 0.1
0.8
11
+0.01
1.0
17
+10
0.3 × V
DD1
V
DD2
0.0
0.15
mA
mA
µA
V
V
V
V
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0 V ≤ V
IA
, V
IB
≤ V
DD1
I
Ox
= −20 mA, V
Ix
= V
IxH
I
Ox
= +20 mA, V
Ix
= V
IxL
V
DD2UV+
V
DD2UV−
V
DD2UVH
V
DD2UV+
V
DD2UV−
V
DD2UVH
I
OA(SC)
, I
OB(SC)
R
OA
, R
OB
R
OA
, R
OB
PW
t
DLH
, t
DHL
t
DLH
, t
DHL
t
PSK
t
PSKCD
t
PSKCD
t
R
/t
F
t
R
/t
F
I
DDI(D)
I
DDO(D)
f
r
3.2
4.1
3.7
0.4
7.0
6.5
0.5
4.0
1.3
0.9
4.4
V
V
V
V
V
V
A
Ω
Ω
ns
MHz
ns
ns
ns
ns
ns
ns
ns
mA/Mbps
mA/Mbps
Mbps
7.5
6.0
2.0
0.3
0.3
50
36
37
3.0
3.0
V
DD2
= 10 V
V
DD2
= 10 V
V
DD2
= 10 V
C
L
= 2 nF, V
DD2
= 10 V
C
L
= 2 nF, V
DD2
= 10 V
C
L
= 2 nF, V
DD2
= 10 V; see Figure 20
C
L
= 2 nF, V
DD2
= 4.5 V; see Figure 20
C
L
= 2 nF, V
DD2
= 10 V; see Figure 20
C
L
= 2 nF, V
DD2
= 10 V; see Figure 20
C
L
= 2 nF, V
DD2
= 4.5 V; see Figure 20
C
L
= 2 nF, V
DD2
= 10 V; see Figure 20
C
L
= 2 nF, V
DD2
= 4.5 V; see Figure 20
V
DD2
= 10 V
V
DD2
= 10 V
48
53
1
1
20
22
0.025
1.5
1.1
14
14
1
62
72
12
5
7
25
28
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 9 and Figure 10 for total V
DD1
and V
DD2
supply currents as a function of frequency.
2
Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
3
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
5
t
DLH
propagation delay is measured from the time of the input rising logic high threshold, V
IH
, to the output rising 10% threshold of the V
Ox
signal. t
DHL
propagation
delay is measured from the input falling logic low threshold, V
IL
, to the output falling 90% threshold of the V
Ox
signal. See Figure 20 for waveforms of propagation
delay parameters.
6
t
PSK
is the magnitude of the worst-case difference in t
DLH
and/or t
DHL
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
7
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
Rev. D | Page 4 of 16
Data Sheet
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input-to-Output)
1
Capacitance (Input-to-Output)
1
Input Capacitance
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
IC Junction-to-Ambient Thermal Resistance
1
ADuM3220/ADuM3221
Symbol
R
I-O
C
I-O
C
I
θ
JCI
θ
JCO
θ
JA
Min
Typ
10
12
1.0
4.0
46
41
85
Max
Unit
Ω
pF
pF
°C/W
°C/W
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center
of package underside
Thermocouple located at center
of package underside
Thermocouple located at center
of package underside
The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
REGULATORY INFORMATION
The
ADuM3220/ADuM3221
are approved by the organizations listed in Table 4.
Table 4.
UL
Recognized Under UL 1577
Component Recognition
Program
1
Single/Basic 2500 V rms
Isolation Voltage
CSA
Approved under CSA Component Acceptance Notice #5A
Basic insulation per CSA 60950-1-03 and IEC 60950-1,
400 V rms (566 V peak) maximum working voltage
Functional insulation per CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage
File 205078
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
2
Reinforced insulation, 560 V peak
File E214100
1
File 2471900-4880-0001
In accordance with UL 1577, each
ADuM3220/ADuM3221
is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection
limit = 5 µA).
2
In accordance with DIN V VDE V 0884-10, each
ADuM3220/ADuM3221
is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial
discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
Symbol
L(I01)
L(I02)
Value
2500
4.90 min
4.01 min
0.017 min
>175
IIIa
Unit
V rms
mm
mm
mm
V
Test Conditions/Comments
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
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