MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC930/931 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock applications. With output frequencies
of up to 150MHz and output skews of 300ps the MPC930/931 is ideal for
the most demanding clock distribution designs. The device employs a
fully differential PLL design to minimize cycle to cycle and long term jitter.
This parameter is of significant importance when the clock driver is
providing the reference clock for PLL’s on board todays microprocessors
and ASiC’s. The device offers 6 low skew outputs, and a choice between
internal or external feedback. The feedback option adds to the flexibility of
the device, providing numerous input to output frequency relationships.
MPC930
MPC931
LOW VOLTAGE
PLL CLOCK DRIVER
•
•
•
•
•
•
•
•
•
On–Board Crystal Oscillator (MPC930)
Differential LVPECL Reference Input (MPC931)
Fully Integrated PLL
Output Shut Down Mode
Output Frequency up to 150MHz
Compatible with PowerPC™ and Intel Microprocessors
32–Lead TQFP Packaging
Power Down Mode
±100ps
Typical Cycle–to–Cycle Jitter
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
The MPC930 and MPC931 are very similar in basic functionality, but
there are some minor differences. The MPC931 has been optimized for
use as a zero delay buffer. In addition to tighter specification limits on the
phase offset of the device, a higher speed VCO has been used on the
MPC931. The MPC930, on the other hand, is more optimized for use as a
clock generator. When choosing between the 930 and 931, pay special
attention to the differences in the AC parameters of each device.
The MPC930/931 offers two power saving features for power conscious portable or “green” designs. The power down pin will
seemlessly reduce all of the clock rates by one half so that the system will run at half the potential clock rate to extend battery life.
The POWER_DN pin is synchronized internally to the slowest output clock rate. This allows the transition in and out of the
power–down mode to be output glitch free. In addition, the shut down control pins will turn off various combinations of clock
outputs while leaving a subset active to allow for total processor shut down while maintaining system monitors to “wake up” the
system when signaled. During shut down, the PLL will remain locked, if internal feedback is used, so that wake up time will be
minimized. The shut down and power down pins can be combined for the ultimate in power savings. The Shut_Dn pins are
synchronized to the clock internal to the chip to eliminate the possibility of generating runt pulses.
The MPC930/931 devices offer a great deal of flexibility in what is used as the PLL reference. The MPC930 offers an
integrated crystal oscillator that allows for an inexpensive crystal to be used as the frequency reference. For more information on
the crystal oscillator please refer to the applications section of this data sheet. In those applications where the 930/931 will be
used to regenerate clocks from an existing source or as a zero delay buffer, alternative reference clock inputs are provided. Both
devices offer an LVCMOS input that can be used as the PLL reference. In addition the MPC931 replaces the crystal oscillator
inputs with a differential PECL reference clock input that allows the device to be used in mixed technology clock distribution trees.
An internal feedback divide by 8 of the VCO frequency is compared with the input reference provided by the on–board crystal
oscillator when the internal feedback is selected. The on–board crystal oscillator requires no external components other than a
series resonant crystal (see Applications Information section for more on crystals). The internal VCO is running at 8x the input
reference clock. The outputs can be configured to run at 4x, 2x, 1.25x or 0.66x the input reference frequency. If the external
feedback is selected, one of the MPC931’s outputs must be connected to the Ext_FB pin. Using the external feedback, numerous
input/output frequency relationships can be developed.
The MPC930/931 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS
or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50Ω transmission
lines. For series terminated applications, each output can drive two 50Ω transmission lines, effectively increasing the fanout to
1:12. The device is packaged in a 32–lead TQFP package to provide the optimum combination of board density and cost.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
1/97
©
Motorola, Inc. 1997
1
REV 3
MPC930 MPC931
ABSOLUTE MAXIMUM RATINGS*
Symbol
VCC
VI
IIN
TStor
Supply Voltage
Input Voltage
Input Current
Storage Temperature Range
–40
Parameter
Min
–0.3
–0.3
Max
4.6
VDD + 0.3
±20
125
Unit
V
V
mA
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
PLL INPUT REFERENCE CHARACTERISTICS
(TA = 0 to 70°C)
Symbol
tr, tf
fref
Characteristic
TCLK Input Rise/Falls
Reference Input Frequency
10
Min
Max
3.0
Note 1.
Unit
ns
MHz
%
Condition
frefDC
Reference Input Duty Cycle
25
75
1. Maximum input reference frequency is limited by the VCO lock range and the feedback divider.
DC CHARACTERISTICS
(TA = 0° to 70°C, VCC = 3.3V
±5%)
Symbol
VIH
VIL
VOH
VOL
IIN
ICC
ICCPLL
CIN
Cpd
25
Characteristic
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Current
Maximum Core Supply Current
Maximum PLL Supply Current
65
15
2.4
0.5
±120
85
20
4
Min
2.0
Typ
Max
3.6
0.8
Unit
V
V
V
V
µA
mA
mA
pF
pF
Per Output
IOH = –20mA (Note 2.)
IOL = 20mA (Note 2.)
Note 3.
Condition
2. The MPC930/931 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
3. Inputs have pull–up/pull–down resistors which affect input current.
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — Rev 6
MPC930 MPC931
MPC930 AC CHARACTERISTICS
(TA = 0° to 70°C, VCC = 3.3V
±5%)
Symbol
fxtal
fref
tos
Characteristic
Crystal Oscillator Frequency Range
Input Reference Frequency
Output–to–Output Skew
(Note 4.)
Same Frequency
Diff Frequency
Same Frequency
Diff Frequency
Power_Dn = 0
Power_Dn = 1
Qa, Qb (÷2)
Qa, Qb, Qc (÷4)
Qc (÷6)
–600
tCYCLE/2
–750
0.1
2.0
2.0
±100
10
–100
tCYCLE/2
±500
100
50
Min
10
Note 7.
200
300
300
450
Typ
Max
20
Note 7.
300
400
400
600
280
140
140
80
47
400
tCYCLE/2
+750
1.0
8.0
10
Unit
MHz
MHz
ps
Condition
Note 5., Note 7.
Ref = TCLK
fmax
≤
100MHz
fmax
≤
100MHz
fmax > 100MHz
fmax > 100MHz
fVCO
fmax
VCO Lock Range
Maximum Output Frequency
MHz
MHz
Note 4.
tpd
tpw
tr, tf
tPLZ, tPHZ
tPZL
tjitter
TCLK to EXT_FB Delay
Output Duty Cycle (Note 4.)
Output Rise/Fall Time (Note 4.)
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter (Peak–to–Peak)
ps
ps
ns
ns
ns
ps
ms
fref = 50MHz, FB =
÷4
0.8 to 2.0V
50Ω to VCC/2
50Ω to VCC/2
Note 6.
tlock
Maximum PLL Lock Time
4. Measured with 50Ω to VCC/2 termination.
5. See Applications Info section for more Crystal specifications.
6. See Applications Info section for more jitter information.
7. Input reference frequency is bounded by VCO lock range and feedback divide selection.
MPC931 AC CHARACTERISTICS
(TA = 0° to 70°C, VCC = 3.3V
±5%)
Symbol
fref
tos
Characteristic
Input Reference Frequency
Output–to–Output Skew
(Note 8.)
Same Frequency
Diff Frequency
Same Frequency
Diff Frequency
Power_Dn = 0
Power_Dn = 1
Qa, Qb (÷2)
Qa, Qb, Qc (÷4)
Qc (÷6)
–150
–400
tCYCLE/2
–750
0.1
2.0
2.0
±100
0
–250
tCYCLE/2
±500
200
100
Min
Note 11.
200
300
300
450
Typ
Max
Note 11.
300
400
400
600
480
240
150
120
80
+150
–100
tCYCLE/2
+750
1.0
8.0
10
Unit
MHz
ps
fmax
≤
100MHz
fmax
≤
100MHz
fmax > 100MHz
fmax > 100MHz
Condition
fVCO
fmax
VCO Lock Range
Maximum Output Frequency
MHz
MHz
Note 9.
tpd
tpw
tr, tf
tPLZ, tPHZ
tPZL
tjitter
Reference to EXT_FB Average Delay TCLK
PECL_CLK
Output Duty Cycle (Note 8.)
Output Rise/Fall Time (Note 8.)
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter (Peak–to–Peak)
ps
ps
ns
ns
ns
ps
fref = 50MHz; FB =
÷8;
Note 12.
0.8 to 2.0V
50Ω to VCC/2
50Ω to VCC/2
Note 10.
tlock
Maximum PLL Lock Time
10
ms
8. Measured with 50Ω to VCC/2 termination.
9. fmax limited by skew spec. Outputs will generate valid CMOS signals up to 180MHz.
10. See Applications Info section for more jitter information.
11. Input reference frequency is bounded by VCO lock range and feedback divide selection.
12. tpd is specified for 50MHz input reference, the window will shrink/grow proportionally from the minimum limit with shorter/linger reference
periods. The tpd does not include jitter.
TIMING SOLUTIONS
BR1333 — Rev 6
5
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