M368L2923CUN-CLCC datasheet, PDF

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M368L2923CUN-CLCC: DescriptionDDR SDRAM Unbuffered Module; File Size445KB，25 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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M368L2923CUN-CLCC Overview

DDR SDRAM Unbuffered Module

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256MB, 512MB, 1GB Unbuffered DIMM

DDR SDRAM

DDR SDRAM Unbuffered Module

184pin Unbuffered Module based on 512Mb C-die

with 64/72-bit ECC/Non ECC

66 TSOP-II with Pb-Free

(RoHS compliant)

Revision 1.0

February. 2005

Rev. 1.0 February. 2005

256MB, 512MB, 1GB Unbuffered DIMM

512Mb C-die Revision History

Revision 0.0 (April, 2004)

- First version for internal review

Revision 0.1 (August, 2004)

- Preliminary spec release.

Revision 0.2 (October, 2004)

- Changed IDD current.

Revision 1.0 (February, 2005)

- Revision 1.0 spec. release.

DDR SDRAM

Rev. 1.0 February. 2005

256MB, 512MB, 1GB Unbuffered DIMM

184Pin Unbuffered DIMM based on 512Mb C-die (x8, x16)

Ordering Information

Part Number

M368L3324CUS-C(L)CC/B3

M368L6523CUS-C(L)CC/B3

M381L6523CUM-C(L)CC/B3

M368L2923CUN-C(L)CC/B3

M381L2923CUM-C(L)CC/B3

Density

256MB

512MB

1GB

Organization

32M x 64

64M x 64

64M x 72

128M x 64

128M x 72

DDR SDRAM

Component Composition

32Mx16 (K4H511638C) * 4EA

64Mx8 (K4H510838C) * 8EA

64Mx8 (K4H510838C) * 9EA

64Mx8 (K4H510838C) * 16EA

64Mx8 (K4H510838C) * 18EA

Height

1,250mil

Operating Frequencies

CC(DDR400@CL=3)

Speed @CL2

Speed @CL2.5

Speed @CL3

CL-tRCD-tRP

166MHz

200MHz

3-3-3

B3(DDR333@CL=2.5)

133MHz

166MHz

2.5-3-3

Feature

• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333

• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided

• SSTL_2 Interface

• 66pin TSOP II

Pb-Free

package

•

RoHS compliant

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 1.0 February. 2005

256MB, 512MB, 1GB Unbuffered DIMM

Pin Configuration (Front side/back side)

Front

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

/CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

Front

DQ24

VSS

DQ25

DQS3

VDD

DQ26

DQ27

VSS

CB0

CB1

VDD

DQS8

CB2

VSS

CB3

BA1

Front

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42

DQ43

VDD

*/CS2

DQ48

DQ49

VSS

/CK2

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

*BA2

DQ20

A12

VSS

DQ21

A11

DM2

VDD

DQ22

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

Back

VSS

DQ28

DQ29

VDDQ

DM3

DQ30

VSS

DQ31

CB4

CB5

VDDQ

CK0

/CK0

VSS

DM8

A10

CB6

VDDQ

CB7

DDR SDRAM

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

/RAS

DQ45

VDDQ

/CS0

/CS1

DM5

VSS

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

*A13

VDD

DM6

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

KEY

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

KEY

VSS

DQ36

DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

Note :

1. * : These pins are not used in this module.

2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module ( M381~ ), and are not used on x64 module.

3. Pins 111, 158 are NC for 1row modules & used for 2row modules[ M368(81)L2923CUN(M) ].

4. Pins 137, 138 are NC for x16 1Row module (M368L3324CUS).

Pin Description

Pin Name

A0 ~ A12

BA0 ~ BA1

DQ0 ~ DQ63

DQS0 ~ DQS8

CK0,CK0 ~ CK2, CK2

CKE0, CKE1(for double banks)

CS0, CS1(for double banks)

RAS

CAS

CB0 ~ CB7 (for x72 module)

Function

Address input (Multiplexed)

Bank Select Address

Data input/output

Data Strobe input/output

Clock input

Clock enable input

Chip select input

Row address strobe

Column address strobe

Write enable

Check bit(Data-in/data-out)

Pin Name

DM0 ~ 7, 8(for ECC)

VDD

VDDQ

VSS

VREF

VDDSPD

SDA

SCL

SA0 ~ 2

Data - in mask

Power supply

(2.5V for DDR333, 2.6V for DDR400)

Power Supply for DQS

(2.5V for DDR333, 2.6V for DDR400)

Ground

Power supply for reference

Serial EEPROM Power/Supply ( 2.3V to 3.6V )

Serial data I/O

Serial clock

Address in EEPROM

No connection

Function

Rev. 1.0 February. 2005

256MB, 512MB, 1GB Unbuffered DIMM

DDR SDRAM

256MB, 32M x 64 Non ECC Module (M368L3324CUS)

(Populated as 1 bank of x16 DDR SDRAM Module)

Functional Block Diagram

CS0

DQS1

DM1

DQ13

DQ14

DQ12

DQ15

DQ9

DQ10

DQ8

DQ11

DQS0

DM0

DQ0

DQ3

DQ4

DQ7

DQ5

DQ2

DQ1

DQ6

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS5

DM5

DQ41

DQ42

DQ45

DQ43

DQ44

DQ46

DQ40

DQ47

DQS0

DM0

DQ32

DQ35

DQ36

DQ39

DQ33

DQ38

DQ37

DQ34

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS3

DM3

DQ29

DQ26

DQ25

DQ30

DQ28

DQ27

DQ24

DQ31

DQS0

DM0

DQ20

DQ23

DQ16

DQ19

DQ17

DQ22

DQ21

DQ18

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS3

DM3

DQ57

DQ62

DQ56

DQ58

DQ61

DQ63

DQ60

DQ59

DQS0

DM0

DQ48

DQ51

DQ52

DQ50

DQ49

DQ55

DQ53

DQ54

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

*Clock Net Wiring

D0/D2

BA0 - BA1

A0 - A12

RAS

CAS

CKE0

BA0-BA1: DDR SDRAMs D0 - D3

Cap

A0-A12: DDR SDRAMs D0 - D3

RAS: DDR SDRAMs D0 - D3

CAS: DDR SDRAMs D0 - D3

CKE: DDR SDRAMs D0 - D3

WE: DDR SDRAMs D0 - D3

Clock Wiring

Clock

DDR SDRAMs

Input

CK0/CK0

CK1/CK1

CK2/CK2

2 DDR SDRAMs

CK1/2

Card

Edge

R=120

Ω

Cap

D1/D3

*If two DRAMs are loaded,

Cap will replace DRAM

Cap

DDSPD

DDQ

SPD

D0 - D3

Serial PD

SCL

SA0

SA1

SA2

SDA

VREF

D0 - D3

Notes:

1. DQ-to-I/O wiring is shown as recomended but

may be changed.

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors: 7.5 Ohms

+ 5%

Rev. 1.0 February. 2005

M368L2923CUN-CLCC Related Products

	M368L2923CUN-CLCC	M368L3324CUS-CLCC	M368L6523CUS-CCC	M368L6523CUS	M381L2923CUM-CCC	M381L6523CUM-CLCC
Description	DDR SDRAM Unbuffered Module	DDR SDRAM Unbuffered Module	DDR SDRAM Unbuffered Module	DDR SDRAM Unbuffered Module	DDR SDRAM Unbuffered Module	DDR SDRAM Unbuffered Module

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