Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Two independent clocked FIFOs buffering data in opposite direc-
tions
•
•
•
•
•
•
•
•
•
•
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
FFA/IRA, EFA/ORA, AEA,
and
AFA
flags synchronized by CLKA
FFB/IRB, EFB/ORB, AEB,
and
AFB
flags synchronized by CLKB
Select IDT Standard timing (using
EFA, EFB, FFA
and
FFB
flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
Available in space-saving 120-pin Thin Quad Flatpack (TQFP)
Pin compatible to the lower density parts, IDT72V3622/72V3632/
72V3642/72V3652/72V3662/72V3672
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA
CSA
W/RA
ENA
MBA
Mail 1
Register
Input
Register
Output
Register
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
RAM
ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
36
Write
Pointer
Read
Pointer
EFB/ORB
AEB
FFA/IRA
AFA
FIFO 1
Status Flag
Logic
FS
0
FS
1
A
0
- A
35
16
Programmable Flag
Offset Registers
FIFO 2
Timing
Mode
FWFT
B
0
- B
35
EFA/ORA
AEA
Status Flag
Logic
Write
Pointer
36
FFB/IRB
AFB
36
Read
Pointer
RAM
ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
Mail 2
Register
Output
Register
FIFO2,
Mail2
Reset
Logic
RST2
Input
Register
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4679 drw 01
MBF2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
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Embedded System
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