M470L3224BT0 datasheet, PDF - EEWORLD Datasheet

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M470L3224BT0: Description256MB DDR SDRAM MODULE; File Size125KB，14 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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M470L3224BT0 Overview

256MB DDR SDRAM MODULE

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M470L3224BT0

200pin DDR SDRAM SODIMM

256MB DDR SDRAM MODULE

(32Mx64 based on 16Mx16 DDR SDRAM)

200pin SODIMM

64-bit Non-ECC/Parity

Revision 0.1

June. 2001

Rev. 0.1 June. 2001

M470L3224BT0

Revision History

Revision 0.0 (Apr. 2001)

1. First release.

200pin DDR SDRAM SODIMM

Revision 0.1 (June. 2001)

1. Changed module current speificaton

2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).

3. Changed AC parameter table.

Rev. 0.1 June. 2001

M470L3224BT0

200pin DDR SDRAM SODIMM

M470L3224BT0 200pin DDR SDRAM SODIMM

32Mx64 200pin DDR SDRAM SODIMM based on 16Mx16

GENERAL DESCRIPTION

The Samsung M470L3224BT0 is 32M bit x 64 Double Data

Rate SDRAM high density memory modules based on first gen

of 256Mb DDR SDRAM respectively.

The Samsung M470L3224BT0 consists of eight CMOS 16M x

16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-

II(400mil) packages mounted on a 200pin glass-epoxy sub-

strate. Four 0.1uF decoupling capacitors are mounted on the

printed circuit board in parallel for each DDR SDRAM.

The M470L3224BT0 is Dual In-line Memory Modules and

intended for mounting into 200pin edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. Data I/O transactions are possible on both

edges of DQS. Range of operating frequencies, programmable

latencies and burst lengths allow the same device to be useful

for a variety of high bandwidth, high performance memory sys-

tem applications.

FEATURE

• Performance range

Part No.

Max Freq.

Interface

SSTL_2

M470L3224BT0-C(L)A2 133MHz(7.5ns@CL=2)

M470L3224BT0-C(L)B0 133MHz(7.5ns@CL=2.5)

M470L3224BT0-C(L)A0 100MHz(10ns@CL=2)

• Power supply : Vdd: 2.5V

0.2V, Vddq: 2.5V

0.2V

•

Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB :

Height 1250 (mil),

double sided component

PIN CONFIGURATIONS (Front side/back side)

Front

VREF

VSS

DQ0

DQ1

VDD

DQS0

DQ2

VSS

DQ3

DQ8

VDD

DQ9

DQS1

VSS

DQ10

DQ11

VDD

CK0

/CK0

VSS

Key

DQ16

DQ17

VDD

DQS2

DQ18

VSS

DQ19

DQ24

VDD

DQ25

DQS3

VSS

DQ26

Front

Back

VREF

VSS

DQ4

DQ5

VDD

DM0

DQ6

VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS

DQ14

DQ15

VDD

VSS

Key

DQ20

DQ21

VDD

DM2

DQ22

VSS

DQ23

DQ28

VDD

DQ29

DM3

VSS

DQ30

Back

DQ38

VSS

DQ39

DQ44

VDD

DQ45

DM5

VSS

DQ46

DQ47

VDD

/CK1

CK1

VSS

DQ52

DQ53

VDD

DM6

DQ54

VSS

DQ55

DQ60

VDD

DQ61

DM7

VSS

DQ62

DQ63

VDD

SA0

SA1

SA2

DQ34

DQ27 135

VSS

137

VDD

DQ35

139

CB0

DQ40

141

CB1

VDD

143

VSS

DQ41

DQS8 145

DQS5

147

CB2

VSS

149

VDD

DQ42

151

CB3

DQ43

153

VDD

155

VSS

VDD

157

CK2

VSS

159

/CK2

VSS

161

VDD

DQ48

CKE1 163

DQ49

97 DU(A13) 165

VDD

167

A12

DQS6

169

101

DQ50

171

VSS

103

VSS

173

105

DQ51

175

107

DQ56

177

109

VDD

179

111

DQ57

181

VDD

113

DQS7

115 A10/AP 183

VSS

185

BA0

117

DQ58

187

/WE

119

DQ59

189

/S0

121

VDD

191

123

SDA

193

VSS

125

SCL

127 DQ32 195

129 DQ33 197 VDDSPD

199 VDDID

VDD

131

133 DQS4

136

DQ31

138

VDD

140

CB4

142

CB5

144

VSS

146

DM8

148

CB6

150

VDD

152

CB7

86 DU/(RESET) 154

156

VSS

158

VSS

160

VDD

162

VDD

164

CKE0

166

DU(BA2)

168

A11

100

170

102

172

VSS

104

174

106

176

108

178

110

180

112

182

VDD

114

184

BA1

116

186

/RAS

118

188

/CAS

120

190

/S1

122

192

124

194

VSS

126

196

DQ36

128

198

DQ37

130

200

VDD

132

DM4

134

PIN DESCRIPTION

Pin Name

A0 ~ A12

BA0 ~ BA1

DQ0 ~ DQ63

DQS0 ~ DQS7

CK0~ CK2,

CK0~ CK2

CKE0

CS0

RAS

CAS

DM0 ~ DM7

VDD

VDDQ

VSS

VREF

VDDSPD

SDA

SCL

SA0 ~ 2

VDDID

Function

Address input (Multiplexed)

Bank Select Address

Data input/output

Data Strobe input/output

Clock input

Clock enable input

Chip select input

Row address strobe

Column address strobe

Write enable

Data - in mask

Power supply (2.5V)

Power Supply for DQS(2.5V)

Ground

Power supply for reference

Serial EEPROM Power

Supply (2.3V to 3.6V)

Serial data I/O

Serial clock

Address in EEPROM

VDD identification flag

No connection

These pins are not used in this module.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.1 June. 2001

M470L3224BT0

FUNCTIONAL BLOCK DIAGRAM

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS2

DM2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS3

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

BA0 - BA1

A0 - A13

RAS

CAS

CKE0

200pin DDR SDRAM SODIMM

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

I/0 7

UDQS

UDM

I/0 8

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 15

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

I/0 7

UDQS

UDM

I/0 8

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 15

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

I/0 7

UDQS

UDM

I/0 8

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 15

DQS4

DM4

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS5

DM5

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS6

DM6

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS7

DM7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

I/0 7

UDQS

UDM

I/0 8

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 15

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

I/0 7

UDQS

UDM

I/0 8

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 15

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

I/0 7

UDQS

UDM

I/0 8

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 15

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

I/0 7

UDQS

UDM

I/0 8

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 15

LDQS

LDM

I/0 0

I/0 1

I/0 2

I/0 3

I/0 4

I/0 5

I/0 6

I/0 7

UDQS

UDM

I/0 8

I/0 9

I/0 10

I/0 11

I/0 12

I/0 13

I/0 14

I/0 15

Dram1

BA0-BA1: DDR SDRAMs D0 - D7

A0-A13: DDR SDRAMs D0 - D7

RAS: SDRAMs D0 - D7

CAS: SDRAMs D0 - D7

CKE: SDRAMs D0 - D7

WE: SDRAMs D0 - D7

Clock

Input

CK0/CK0

CK1/CK1

CK2/CK2

Clock Wiring

SDRAMs

4 SDRAMs

Card

Edge

*Clock Net Wiring

R=120

Ω

Dram2

Dram3

Dram4

DDSPD

DDQ

SPD

D0 - D7

SCL

Serial PD

SDA

SA0

SA1

SA2

VREF

DDID

D0 - D7

Strap: see Note 4

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD

≠

VDDQ.

Rev. 0.1 June. 2001

M470L3224BT0

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Voltage on V

DDQ

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

, V

OUT

DDQ

STG

200pin DDR SDRAM SODIMM

Value

-0.5 ~ 3.6

-1.0 ~ 3.6

-0.5 ~ 3.6

-55 ~ +150

Unit

°C

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 70°C)

Parameter

Supply voltage(for device with a nominal V

of 2.5V)

I/O Supply voltage

I/O Reference voltage

I/O Termination voltage(system)

Input logic high voltage

Input logic low voltage

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

Input crossing point voltage, CK and CK inputs

Input leakage current

Output leakage current

Output High Current(Normal strengh driver)

OUT

= V

+ 0.84V

Output High Current(Normal strengh driver)

OUT

= V

- 0.84V

Output High Current(Half strengh driver)

OUT

= V

+ 0.45V

Output High Current(Half strengh driver)

OUT

= V

- 0.45V

Symbol

DDQ

REF

(DC)

Min

2.3

VDDQ/2-50mV

REF

-0.04

REF

+0.15

-0.3

0.3

1.15

-2

-5

-16.8

16.8

-9

Max

2.7

VDDQ/2+50mV

REF

+0.04

DDQ

+0.3

REF

-0.15

DDQ

+0.3

DDQ

+0.6

1.35

Unit

Note

Notes

1. Includes

25mV margin for DC offset on V

REF

, and a combined total of

50mV margin for all AC noise and DC offset on V

REF

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V

REF

and internal DRAM noise coupled

TO V

REF

, both of which may result in V

REF

noise. V

REF

should be de-coupled with an inductance of

≤

3nH.

2.V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to

REF

, and must track variations in the DC level of V

REF

3. V

is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

5. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

Rev. 0.1 June. 2001

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Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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