IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH162244A
3.3V CMOS 16-BIT
BUFFER/DRIVER WITH 3-STATE
OUTPUTS, 5 VOLT TOLERANT I/O,
AND BUS-HOLD
FEATURES:
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
μ
• All inputs, outputs, and I/O are 5V tolerant
• Available in TSSOP and TVSOP packages
DESCRIPTION:
The LVCH162244A 16-bit buffer/driver is built using advanced dual
metal CMOS technology. The LVCH162244A is designed specifically to
improve both the performance and density of 3-state memory address
drivers, clock drivers, and bus-oriented receivers and transmitters. The
device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
This device provides true outputs and symmetrical active-low output-enable
(OE) inputs.
All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V
devices. This feature allows the use of this device as a translator in a mixed
3.3V/5V supply system.
The LVCH162244A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been developed to drive ±12mA at the designated threshold
levels.
The LVCH162244A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Full internal series termination
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
3
OE
25
1
A
1
47
2
1
Y
1
3
A
1
36
13
3
Y
1
1
A
2
46
3
1
Y
2
3
A
2
35
14
3
Y
2
1
A
3
44
5
1
Y
3
3
A
3
33
16
3
Y
3
1
A
4
43
6
1
Y
4
3
A
4
32
17
3
Y
4
2
OE
48
4
OE
24
2
A
1
41
8
2
Y
1
4
A
1
30
19
4
Y
1
2
A
2
40
9
2
Y
2
4
A
2
29
20
4
Y
2
2
A
3
38
11
2
Y
3
4
A
3
27
22
4
Y
3
2
A
4
37
12
2
Y
4
4
A
4
26
23
4
Y
4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2006 Integrated Device Technology, Inc.
February 20, 2009
DSC-4727/5
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
Y
1
1
Y
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
Max
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
Unit
V
°C
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
OE
1
A
1
1
A
2
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GND
1
Y
3
1
Y
4
GND
1
A
3
1
A
4
V
CC
2
Y
1
2
Y
2
V
CC
2
A
1
2
A
2
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
GND
2
Y
3
2
Y
4
3
Y
1
3
Y
2
GND
2
A
3
2
A
4
3
A
1
3
A
2
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
GND
3
Y
3
3
Y
4
NOTE:
1. As applicable to the device type.
GND
3
A
3
3
A
4
PIN DESCRIPTION
Pin Names
xOE
xAx
xYx
Data Inputs
(1)
3-State Outputs
Description
3-State Output Enable Inputs (Active LOW)
V
CC
4
Y
1
4
Y
2
V
CC
4
A
1
4
A
2
GND
4
Y
3
4
Y
4
4
OE
GND
4
A
3
4
A
4
3
OE
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE
(EACH 4-BIT BUFFER)
(1)
Inputs
xOE
xAx
L
H
X
Outputs
xYx
L
H
Z
TSSOP/ TVSOP
TOP VIEW
L
L
H
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
Parameter
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
ΔI
CC
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
—
—
—
—
—
—
—
–0.7
100
—
—
—
±50
–1.2
—
10
10
500
µA
V
mV
µA
V
CC
= 3.6V
V
O
= 0 to 5.5V
—
—
±10
µA
Input LOW Voltage Level
Input Leakage Current
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
Test Conditions
Min.
1.7
2
—
—
—
Typ.
(1)
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
µA
V
Unit
V
Quiescent Power Supply Current
Variation
3.6
≤
V
IN
≤
5.5V
(2)
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
—
—
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
3
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per Buffer/Driver Outputs enabled
Power Dissipation Capacitance per Buffer/Driver Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
35
4
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK
(o)
Parameter
Propagation Delay
xAx to xYx
Output Enable Time
xOE to xYx
Output Disable Time
xOE to xYx
Output Skew
(2)
Min.
Max.
5.6
6.9
6.8
V
CC
= 3.3V ± 0.3V
Min.
1.1
1
1.8
Max.
4.4
5.5
6.3
500
Unit
ns
ns
ns
ps
—
—
—
—
—
—
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
= 3.3V±0.3V
6
2.7
1.5
300
300
50
(1)
V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
(2)
Unit
V
V
V
mV
mV
pF
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC Link
Propagation Delay
V
CC
500Ω
Pulse
(1, 2)
Generator
V
IN
D.U.T.
R
T
500Ω
C
L
LVC Link
V
LOAD
Open
GND
V
OUT
CONTROL
INPUT
ENABLE
DISABLE
t
PZL
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
LVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC Link
INPUT
t
PLH1
t
PHL1
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
LVC Link
V
T
OUTPUT 1
t
SK
(x)
t
SK
(x)
OUTPUT 2
t
PLH2
t
PHL2
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Pulse Width
LVC Link
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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