CCD Delay Line Series
MN3885S
NTSC-Compatible CCD Video Signal Delay Element
Overview
The MN3885S is a CCD signal delay element for video
signal processing applications.
It contains such components as a shift register clock
driver, charge I/O blocks, two CCD delay elements, a
clamp bias circuit, resampling output amplifiers, and
booster circuits.
The MN3885S samples the input using the supplied
clock signal with a frequency 7.15909 MHz of twice the
NTSC color signal subcarrier frequency, and after add-
ing in the attached filter delay, produces independent de-
lays of 1 H (the horizontal scan period) each for the two
lines.
Pin Assignment
VOC
V
DD
V
SS
VOY
1
2
3
4
8
7
6
5
VINC
XI
V
BB
VINY
( TOP VIEW )
SOP008-P-0225A
Features
Single 5.0 V power supply
Single chip combining luminance signal delay line and
delay line for color signal converted to the low fre-
quency.
Low EMI levels from clock during driving
Applications
VCRs, Video cameras
Structure and Operation
The MN3885S consists of the operational blocks shown
in the block diagram. The shift register has the structure
shown in the supplementary diagram.
Shift register clock driver
This block generates two transfer clock signals, ø1 and
ø2, synchronized with the 7.15909 MHz input clock sig-
nal.
It also generates the sampling clock signals øS and øS',
resampling clock signal øSH, and reset clock signal øR
based on the timing control.
Charge Input blocks
These blocks alter the analog input signals from the
VINC and VINY pins on their way to the shift registers.
One adds the bias voltage specified with the bias circuit
to the analog signal from the VINC pin. The other ap-
plies an "L" level clamp voltage from the clamp circuit
to the analog signal from the VINY pin.
Analog shift registers
These blocks sample the shift register input signals with
the sampling clock, and convert the results to charges,
and use transfer clocks ø1 and ø2 to transfer the results to
the following block.
Charge detection blocks
These convert the signal charges from the final stage
of the analog shift registers into voltage signals.
Resampling output amplifiers
In the output stage of this blocks, the voltage signal is
executed Sample-and-Hold by resampling, and is output-
ted at signal output pin of VOC (1-pin) and VOY (4-pin).
Bias circuit
This circuit applies a bias voltage to the analog signal
from VINC (pin 8) to optimize it for the shift register.
Clamp circuit
This circuit applies an "L" level clamp to the analog
signal from VINY (pin 5) to optimize it for the shift reg-
ister.
Booster circuits
These generate reset drain voltages.
1
CCD Delay Line Series
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
Symbol
VOC
V
DD
V
SS
VOY
VINY
V
BB
XI
VINC
Pin Name
Signal output (C)
Power supply
Ground
Signal output (Y)
Signal input (Y)
Substrate connection
Clock input
Signal input (C)
MN3885S
Remarks
Negative voltage pin
Operating Conditions
Parameter
Power supply
Input clock frequency
Input clock amplitude (sine wave)
Ambient temperature
Symbol
V
DD
f
ck
v
ck
Ta
0.2
–20
min
4.75
typ
5.00
7.15909
0.3
1.5
60
max
5.25
Unit
V
MHz
V
P–P
˚C
Electrical Characteristics
V
DD
=5.0V, V
ck
=0.3V
P-P
(sine wave), V
in
=0.5V
P-P
(sine wave), f
ck
=7.15909MHz, Ta=25˚C
Parameter
Power supply voltage
Signal bandwidth (Y signal)
Signal bandwidth (C signal)
Insertion gain (Y signal)
Insertion gain (C signal)
Total harmonic distortion
Signal-to-noise ratio
Clock leak
Crosstalk
Delay (Y signal)
Delay (C signal)
VO pin output impedance
Input bias voltage
Input clamp voltage
Output bias voltage
Output clamp voltage
Substrate voltage
Symbol
Conditions
min
1.8
1.8
0.0
–1.0
48
I
DD
BWY –3 dB for 200 kHz value
BWC –3 dB for 200 kHz value
IGY
IGC
S/N
NC
CT
τ
DY
τ
DC
Z
OY
Z
OC
V
BIN
Applied to input from C signal input pin
V
CLIN
Applied to input from Y signal input pin
V
BO
–V
BB
Applied to output from C signal output pin
typ
18
2.8
2.8
3.0
2.0
1.0
56
–30
–50
63.38
63.46
0.5
0.5
2.86
2.70
2.70
2.40
–2.80
max
36
Unit
mA
MHz
f
sig
=200kHz
f
sig
=200kHz
Signal output (V
p-p
)/noise output (rms)
7.16 MHz components for both
Y and C signals
f
sig
=200kHz
6.0
5.0
4.5
dB
%
dB
THD f
sig
=200kHz
–10
–35
dB
dB
µs
0.9
0.9
kΩ
V
V
V
V
V
V
CLO
Applied to output from Y signal output pin
3
Embedded System
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