MM74HC175 Quad D-Type Flip-Flop With Clear
September 1983
Revised February 1999
MM74HC175
Quad D-Type Flip-Flop With Clear
General Description
The MM74HC175 high speed D-type flip-flop with comple-
mentary outputs utilizes advanced silicon-gate CMOS
technology to achieve the high noise immunity and low
power consumption of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
Information at the D inputs of the MM74HC175 is trans-
ferred to the Q and Q outputs on the positive going edge of
the clock pulse. Both true and complement outputs from
each flip flop are externally available. All four flip-flops are
controlled by a common clock and a common CLEAR.
Clearing is accomplished by a negative pulse at the
CLEAR input. All four Q outputs are cleared to a logical “0”
and all four Q outputs to a logical “1.”
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 15 ns
s
Wide operating supply voltage range: 2–6V
s
Low input current: 1
µA
maximum
s
Low quiescent supply current: 80
µA
maximum (74HC)
s
High output drive current: 4 mA minimum (74HC)
Ordering Code:
Order Number
MM74HC175M
MM74HC175SJ
MM74HC175MTC
MM74HC175N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
(Each Flip-Flop)
Inputs
Outputs
Clear
L
H
H
H
Clock
X
↑
↑
L
D
X
H
L
X
Q
L
H
L
Q
0
Q
H
L
H
Q
0
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Irrelevant
↑ =
Transition from LOW-to-HIGH level
Q
0
=
The level of Q before the indicated steady-state input conditions were
established
Top View
© 1999 Fairchild Semiconductor Corporation
DS005319.prf
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MM74HC175
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260°C
600 mW
500 mW
−0.5
to
+7.0V
−1.5
to V
CC
+1.5V
−0.5
to V
CC
+0.5V
±20
mA
±25
mA
±50
mA
−65°C
to
+150°C
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
,V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
0
−40
V
CC
+85
V
°C
2
Max
6
Units
V
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
Conditions
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
6.0V
V
IN
=
V
CC
or GND
4.5V
6.0V
6.0V
4.5V
6.0V
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC175
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
REC
t
S
t
H
t
W
Parameter
Maximum Operating
Frequency
Maximum Propagation
Delay, Clock to Q or Q
Maximum Propagation
Delay, Reset to Q or Q
Minimum Removal
Time, Clear to Clock
Minimum Setup Time, Data to Clock
Minimum Hold Time, Data from Clock
Minimum Pulse Width, Clock or Clear
10
20
0
16
ns
ns
ns
20
ns
13
21
ns
15
25
ns
Conditions
Typ
60
Guaranteed
Limit
35
Units
MHz
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
f
MAX
Parameter
Maximum Operating
Frequency
t
PHL
, t
PLH
Maximum Propagation
Delay, Clock to Q or Q
t
PHL
, t
PLH
Maximum Propagation
Delay, Reset to Q or Q
t
REM
Minimum Removal Time
Clear to Clock
t
S
Minimum Setup Time
Data to Clock
t
H
Minimum Hold Time
Data from Clock
t
W
Minimum Pulse Width
Clear or Clock
t
r
, t
f
Maximum Input Rise and
Fall Time
t
TLH
, t
THL
Maximum
Output Rise and
Fall Time
C
PD
C
IN
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
=C
PD
V
CC2
f+I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=C
PD
V
CC
f+I
CC
.
Conditions
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
=
25°C
Typ
12
60
70
80
15
13
64
14
12
6
30
35
150
30
26
125
25
21
100
20
17
100
20
17
0
0
0
30
9
8
80
16
14
1000
500
400
30
9
8
150
5
10
75
15
13
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
5
24
28
190
38
32
158
32
27
125
25
21
125
25
21
0
0
0
100
20
17
1000
500
400
95
19
16
4
20
24
225
45
38
186
37
32
150
30
25
150
30
25
0
0
0
120
24
20
1000
500
400
110
22
19
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
(per package)
10
10
pF
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