Product Data Sheet
FX-700
Low Jitter Frequency Translator
Features
•
•
•
•
•
•
•
•
•
5.0 x 7.5 mm, Hermetically sealed SMD package
Frequency Translation to 77.760 MHz
3.3 Volt or 5.0 Volt Supply
Tri-State Output allows board test
Lock Detect
Commercial or Industrial Temp. Range
CMOS Output
Absolute Pull Range Performance to +/-100 ppm
Capable of locking to an 8 kHz pulse/BITS clock
Description
The FX-700 is a crystal-based frequency translator
used in communications applications where low jit-
ter is paramount.
Performance advantages include superior jitter
performance, high output frequencies and small
package size. Advanced custom ASIC technology
results in a highly robust, reliable and predictable
device. The device is packaged in a 16 pad ceram-
ic package with a hermetic seam welded lid.
External Loop Filter
Applications
•
•
•
•
•
Frequency Translation, Clock Smoothing
Telecom - SONET/SDH/ATM
Datacom – DSLAM, DSLAR, Access Nodes
Base Station – GSM, CDMA
Cable Modem Head End
R2
C2
C1
C1 Charge
Pump Out
(5)
LD
(8)
F
IN
(6)
Input Frequency
Divider (1-64)
Charge
Pump
V
COUT
(3)
V
CIN
(16)
Phase/Freq.
Detector
Buffer
VCXO
VCXO
OUT
(13)
FX-700
Output Frequency
Divider (1-16384)
Buffer
GND
(7)
V
DD
(1)
V
DB
(11)
GND
B
(9)
V
DA
(2)
Tri-State
(4)
F
OUT
(10)
VCXO
IN
(12)
V
DO
(14)
Figure 1. FX-700 Block Diagram
FX-700 Low Jitter Frequency Translator
Performance Characteristics
Electrical Performance
Parameter
Output Frequency
4
Output (3.3 V)
Output (5.0 V)
Supply Voltage
1
(V
DD
,V
DB
,V
DA
,V
DO
)
+5.0
+3.3
Supply Current
5
@19.440 MHz
49.152 MHz
77.760 MHz
Output
2
Output High
Output Low
Transition Times
2
Rise Time
Fall Time
Duty Cycle
3
<60 MHz
≥60
MHz
Absolute Pull Range
Operating Temperature:
Test Conditions for APR (+5V option)
Test Conditions for APR (+3.3V option)
Input
Frequency
Pulse Width
Low Logic Level
High Logic Level
Jitter, 8kHz to 77.760 MHz
6
rms
peak/peak
peak/peak
Leakage Current of Input
Size
Symbol
fo
fo
V
DD
V
DD
I
DD
I
DD
I
DD
V
OH
V
OL
t
R
t
F
D
APR
V
C
V
C
f
IN
V
IL
V
IH
Minimum
0.100
0.100
4.5
2.97
5.0
3.3
15
25
35
Typical
Maximum
77.760
77.760
5.5
3.63
20
30
40
Units
MHz
MHz
V
V
mA
mA
mA
V
V
ns
ns
%
%
ppm
V
V
0.9*Vdd
0.1*Vdd
1.8
3.0
1.8
3.0
45
50
55
40
50
60
See Part Numbering
0 to 70°C or -40 to 85°C
0.5
4.5
0.3
3.0
1 kHz
6.0
0.7* Vdd
4.7
44
0.003
77.76 MHz
0.3* Vdd
ns
V
V
ps
ps
UI
uA
IC
-1
+1
5.0mm x 7.5mm x 2.0mm
1. A 0.01uF high frequency ceramic capacitor in parallel with a 0.1uF low frequency tantalum bypass capacitor is recommended
2. Figure 2 defines the waveform parameters. Figure 3 illustrates the standard test conditions under which these parameters are tested and specified
3. Duty Cycle is defined as (on time/period) with Vs = Vdd/2 per Figure 2. Duty Cycle is measured with a 15pf load per Figure 3.
4. Other frequencies may be available, please contact factory.
5. Combined Current From V
DD
, V
DO
, V
DA
, and V
DB
6. Typical jitter for 8 kHz to 77.760 MHz translation (no offset bandwidth).
t
R
80
%
t
F
I
D D
30k
2k
Vs
20
%
On Time
Period
V
D D
+
-
.
1uF
.01uF
2,14,11,1 8 13,12 10
15 6 4 7,9 3,16
5
n/c
R2
f
IN
C1
C2
15pF
Figure 2. Output Waveform
Figure 3. Output Test Conditions (25
±5°C)
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Web: www.vectron.com
2
FX-700 Low Jitter Frequency Translator
Outline Diagram
13 12 11 10 9
14
15
16
FLACGNK
A3/K2
VI YWW
1 2 3 4 5
8
7
6
Pin Out
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
V
DD
V
DA
V
COUT
Tri-state
1
C1
F
IN
GND
LD
2
GND
B
F
OUT
V
DB
VCXO
IN
VCXO
OUT
V
DO
N.C.
VC
IN
Function
Digital PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
Analog PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
Control Voltage
Logic Low = Output Disable / Logic High = Output Enabled
Passive Loop Filter Node
Input Frequency
Cover and Electrical Ground
Lock Detect
Output Buffer Ground
Output Frequency
Output Buffer Supply (3.3V +/-10% or 5.0V +/-10%)
VCXO Input
VCXO Output
VCXO Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
No Internal Connection Made
VCXO Control Voltage Input
1 Tri-state must be driven to a logic high or a logic low, there is no internal pull up or pull down resistor (tie pin to VDD for
PLL operation).
2 LD is an open collector output requiring a 30k ohm minimum pull-up resistor to VDD. LD output is logic high under
locked condition, logic low for no input at FIN, and for "out-of-lock" condition LD transitions between logic low and high
at the phase detector frequency.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Web: www.vectron.com
3
FX-700 Low Jitter Frequency Translator
Solder Pad Layout
J
F
D
A
E
C
G
B
L
I
H
K
Tape and Reel Dimensions (mm)
Tape Dimensions
Product
FX-700
A
16
B
7.5
C
1.5
D
4
E
8
Reel Dimensions
F
1.5
G
20.2
H
13
I
50
J
6
K
16.4
L
178
500
# Per Reel
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Web: www.vectron.com
4
FX-700 Low Jitter Frequency Translator
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is
not implied at these or any other conditions in excess of conditions represented in the operational sections of this
data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability.
Parameter
Power Supply
Storage Temperature
Symbol
V
DD
Tstorage
Ratings
7
-55/125
Unit
Vdc
°C
Reliability
Absolute Maximum Ratings
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883 Method 2002
MIL-STD-883 Method 2007
MIL-STD-883 Method 2003
MIL-STD-883 Method 1014
MIL-STD-883 Method 2016
Handling Precautions
Although ESD protection circuitrry has been designed into the the FX-700, proper precautions should be taken
when handling and mounting. VI employs a human body model and a charged-device model (CDM) for ESD sus-
ceptibility testing and design protection evaluation. ESD thresholds are dependent on the circuit parameters used
to define the model. Although no industry wide standard has been adopted for the CDM, a standard HBM of resist-
ance=1.5Kohms and capacitance = 100pF is widely used and Therefore can be used for comparison purposes.
ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
1500
1000
Conditions
MIL-STD-883, Method 3015
JESD 22-C101
Recommended Solder Reflow Profile
Times(s)
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Web: www.vectron.com
5
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