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ML6554
3A Bus Termination Regulator
Features
• Can source and sink up to 3A, no heat sink required
• Integrated Power MOSFETs
• Generates termination voltages for DDR SDRAM,
SSTL-2 SDRAM, SGRAM, or equivalent memories
• Generates termination voltages for active termination
schemes for DDR SDRAM, GTL+, Rambus, VME,
LV-TTL, HSTL, PECL and other high speed logic
• V
REF
input available for external voltage divider
• Separate voltages for V
CCQ
and PV
DD
• Buffered V
REF
output
• V
OUT
of ±3% or less at 3A
• Minimum external components
• Shutdown for standby or suspend mode operation
• 0° to +70°C and -40° to +85°C temperature ranges
available
• Thermal Shutdown
≈
130ºC
Description
The ML6554 switching regulator is designed to convert volt-
age supplies ranging from 2.3V to 4V into a desired output
voltage or termination voltage for various applications. The
ML6554 can be implemented to produce regulated output
voltages in two different modes. In the default mode, when
the V
REF
pin is open, the ML6554 output voltage is 50% of
the voltage applied to V
CCQ
. The ML6554 can also be used
to produce various user-defined voltages by forcing a voltage
on the VREF
IN
pin. In this case, the output voltage follows
the input VREF
IN
voltage. The switching regulator is capa-
ble of sourcing or sinking up to 3A of current while regulat-
ing an output V
TT
voltage to within 3% or less.
The ML6554, used in conjunction with series termination
resisitors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator can
be used as a termination voltage for other bus interface
standards such as DDR SDRAM, SSTL, CMOS, Rambus
™
,
GTL+, VME, LV-CMOS, LV-TTL, HSTL and PECL.
Block Diagram
15
VCCQ
16
AVCC
14
VREFOUT
1
9
VDD
VDD
12
SHDN
2
PVDD1
7
PVDD2
VL1
(VOUT)
3
OSCILLATOR/
RAMP
GENERATOR
–
200kΩ
+
VREF BUFFER
VREFIN
11
200kΩ
AGND
13
+
–
–
R
+
ERROR AMP
RAMP
COMPARATOR
Q
S
Q
6
VL2
(VOUT)
VFB
10
8
DGND
4
PGND1
5
PGND2
REV. 1.1.3 3/8/02
ML6554
PRODUCT SPECIFICATION
Pin Configuration
ML6554
16-Pin PSOP (U16)
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
TOP VIEW
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
V
DD
PV
DD1
V
L1
P
GND1
P
GND2
V
L2
PV
DD2
D
GND
V
DD
V
FB
VREF
IN
SHDN
AGND
VREF
OUT
V
CCQ
AV
CC
Digital supply voltage
Voltage supply for internal power transistors
Output voltage/ inductor connection
Ground for output power transistors
Ground for output power transistors
Output voltage/inductor connection
Voltage supply for internal power transistors
Digital ground
Digital supply voltage
Input for external compensation feedback
Input for external reference voltage
Shutdown active low. CMOS input level
Ground for internal reference voltage divider
Reference voltage output
Voltage reference for internal voltage divider
Analog voltage supply
Function
2
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
PV
DD
Voltage on Any Other Pin
Average Switch Current (I
AVG
)
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance (
θ
JC
)(Note 2)
Output Current, Source or Sink
Min.
GND – 0.3
Max.
4.5
V
IN
+ 0.3
3.0
150
150
150
2
3.0
Units
V
V
A
°C
°C
°C
°C/W
A
-65
Operating Conditions
Parameter
Temperature Range, CU suffix
Temperature Range, IU suffix
PV
DD
Operating Range
V
CCQ
Operating Range
Min.
0
-40
2.0
1.4
Max.
70
+85
4.0
4.0
Units
°C
°C
V
V
Electrical Characteristics
Unless otherwise specified, AV
CC
= V
DD
= PV
DD
= 3.3V ±10%, TA = Operating Temperature Range (Note 1)
Symbol
Parameter
Switching Regulator
V
TT
Output Voltage, SSTL_2
(See Figure 1)
Conditions
I
OUT
= 0,
V
REF
= open
I
OUT
= ±3A,
V
REF
= open
VREF
OUT
Internal Resistor Divider
I
OUT
= 0
Min.
Typ.
Max. Units
V
V
V
V
V
V
V
V
V
k
Ω
kHz
mV
µA
mA
mA
mA
mA
µA
mA
Z
IN
V
REF
Reference Pin Input
Impedance
Switching Frequency
Offset Voltage V
TT
– VREF
OUT
V
CCQ
= 2.3V 1.12 1.15 1.18
V
CCQ
= 2.5V 1.22 1.25 1.28
V
CCQ
= 2.7V 1.32 1.35 1.38
V
CCQ
= 2.3V 1.09 1.15 1.21
V
CCQ
= 2.5V 1.19 1.25 1.31
V
CCQ
= 2.7V 1.28 1.35 1.42
V
CCQ
= 2.3V 1.139 1.15 1.162
V
CCQ
= 2.5V 1.238 1.25 1.263
V
CCQ
= 2.7V 1.337 1.35 1.364
100
V
CCQ
= 0
650
∆
V
OFFSET
Supply
I
Q
Quiescent Current
AV
CC
= 2.5V No Load V
CCQ
= 2.5
I
OUT
= 0, no load
V
CCQ
= 2.5V
I
VCCQ
I
AVCC
I
AVCC
SD
I
VDD
I
VDD
SD
I
PVDD
–20
6
0.5
0.2
0.25
0.2
100
3
20
10
1.0
0.5
1.0
1.0
250
Buffer
I
REF
Output Load Current
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Infinite heat sink
REV. 1.1.3 3/8/02
3
ML6554
PRODUCT SPECIFICATION
Functional Description
This switching regulator is capable of sinking and sourcing
3A of current without an external heatsink. The ML6554
uses a power surface mount package (PSOP) that includes
an integrated heat slug. The heat can be piped through the
bottom of the device and onto the PCB (Figure 1).
The ML6554 integrates two power MOSFETs that can be
used to source and sink 3A of current while maintaining a
tight voltage regulation. Using the external feedback, the
output can be regulated well within 3% or less, depending on
the external components chosen. Separate voltage supply
inputs have been added to accommodate applications with
various power supplies for the databus and power buses, see
Figure 2.
Output voltage can also be selected by forcing a voltage at
the VREF
IN
pin. In this case, the output voltage follows the
voltage at the VREF
IN
input. Simple voltage dividers can be
used this case to produce a wide variety of output voltages
between 0.7V and V
DD
–0.7V.
VREF Input and Output
The VREF
IN
input can be used to force a voltage at the
outputs (Inputs section, above). The VREF
OUT
pin is an
output pin that is driven by a small output buffer to provide
the V
REF
signal to other devices in the system. The output
buffer is capable of driving several output loads. The output
buffer can handle 3mA.
Other Supply Voltages
Several inputs are provide for the supply voltages: PV
DD1
,
PV
DD2
, AV
CC
, and V
DD
.
The PV
DD1
and PV
DD2
provide the power supply to the
power MOSFETs. V
DD
provides the voltage supply to the
digital sections, while AV
CC
supplies the voltage for the
analog sections. Again, see the Applications section for
recommendations.
Outputs
The output voltage pins (V
L1
, V
L2
) are tied to the databus,
address, or clock lines via an external inductor. See the
Applications section for recommendations. Output voltage
is determined by the V
CCQ
or VREF
IN
inputs.
Inputs
The input voltage pins (V
CCQ
or VREF
IN
) determine the
output voltages (V
L1
or V
L2
) . In the default mode, where
the VREF
IN
pin is floating, the output voltage is 50% of the
V
CCQ
input. V
CCQ
can be the reference voltage for the
databus.
Feedback Input
The V
FB
pin is an input that can be used for closed loop
compensation. This input is derived from the voltage output.
See application section for recommendation.
HEAT SLUG
Figure 1. Cutaway view of PSOP Package
4
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Applications
Using the ML6554 for SSTL Bus Termination
The circuit schematic in Figure 2 shows a recommended
approach for constructing a bus terminating solution for an
SSTL-2 bus. This circuit can be used in PC memory and
Graphics memory applications as shown in Figures 4 and 5.
Note that the ML6554 can provide the voltage reference
(V
REF
) and terminating voltages (V
TT
). Using the layout
as shown in Figures 6, 7, and 8, and measuring the V
TT
performance using the test setup as described in Figure 9,
the ML6554 delivered a V
TT
± 20mV for 1A to 3A loads
(see Figure 10). Table 1 provides a recommended parts list
for the circuit in Figure 2.
Power Handling Capability of the PSOP
Package
Using the board layout shown in Figures 6, 7, and 8; solder-
ing the ML6554 to the board at zero LFPM the temperature
around the package measured 55ºC for 3A loads. Note that a
1 ounce copper plane was used in the board construction.
Airflow is not likely to be needed in the operation of this
device (assuming a board layout similar to that described
above). The power handling performance of the PSOP
package is shown by a study of the package manufacturer for
various airflow vs.
θ
JA
conditions in Figure 11.
Bus Termination Solutions for Others Buses
Table 3 provides a summary of various bus termination V
REF
& V
TT
requirements. The ML6554 can be used for those
applications.
2.5V TO 4V
R2 100Ω
R1 100Ω
C9 0.1µF
C8 0.1µF
R3
100kΩ
C5
330µF
C6
330µF
U1
ML6554
TPI
1
2
VTT
C1
820µF
F2V
OS-CON
TO SDRAMS
L1 3.3µH C3 0.1µF
3
4
C2
0.1µF
C4 0.1µF
5
6
7
8
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
16
15
14
13
12
11
10
9
SHDN
VREFIN
VCCQ
VREFOUT
R4 100kΩ
C7 1nF
GND
R5 1kΩ
GND
Figure 2.
REV. 1.1.3 3/8/02
5
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