74HC595DB datasheet, PDF - EEWORLD Datasheet

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74HC595DB: DescriptionSerial In Parallel Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16; Categorylogic logic; File Size251KB，24 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74HC595DB Overview

Serial In Parallel Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16

74HC595DB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	SSOP-16
Reach Compliance Code	compliant
Other features	SERIAL STANDARD OUTPUT FOR CASCADING
Counting direction	RIGHT
series	HC/UH
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	6.2 mm
Logic integrated circuit type	SERIAL IN PARALLEL OUT
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	265 ns
Certification status	Not Qualified
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	5.3 mm
minfmax	24 MHz
Base Number Matches	1

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74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output

latches; 3-state

Rev. 7 — 26 January 2015

Product data sheet

1. General description

The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible

with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC

standard No. 7A.

The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and

3-state outputs. The registers have separate clocks.

Data is shifted on the positive-going transitions of the shift register clock input (SHCP).

The data in each register is transferred to the storage register on a positive-going

transition of the storage register clock input (STCP). If both clocks are connected together,

the shift register will always be one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.

It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The

storage register has 8 parallel 3-state bus driver outputs. Data in the storage register

appears at the output whenever the output enable input (OE) is LOW.

2. Features and benefits



8-bit serial input

8-bit serial or parallel output

Storage register with 3-state outputs

Shift register with direct clear

100 MHz (typical) shift out frequency

ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Multiple package options



Specified from

40 C

to +85

C

and from

40 C

to +125

C

3. Applications



Serial-to-parallel data conversion



Remote control holding register

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