SiC769
Vishay Siliconix
Integrated DrMOS Power Stage
DESCRIPTION
The SiC769CD is an integrated solution that contains PWM
optimized n-channel MOSFETs (high side and low side) and
a full featured MOSFET driver IC. The device complies with
the Intel DrMOS standard for desktop and server V
core
power
stages. The SiC769CD delivers up to 35 A continuous output
current and operates from an input voltage range of 3 V to
16 V. The integrated MOSFETs are optimized for output
voltages in the ranges of 0.8 V to 2 V with a nominal input
voltage of 12 V. The device can also deliver very high power
at 5 V output for ASIC applications.
The SiC769CD incorporates an advanced MOSFET gate
driver IC. This IC accepts a single PWM input from the V
R
controller and converts it into the high side and low side
MOSFET gate drive signals. The driver IC is designed to
implement the skip mode (SMOD) function for light load
efficiency improvement. Adaptive dead time control also
works to improve efficiency at all load points. The SiC769CD
has a thermal warning (THDN) that alerts the system of
excessive junction temperature. The driver IC includes an
enable pin, UVLO and shoot through protection.
The SiC769CD is optimized for high frequency buck
applications. Operating frequencies in excess of 1 MHz can
easily be achieved.
The SiC769CD is packaged in Vishay Siliconix high
performance PowerPAK MLP6 x 6 package. Compact
co-packaging of components helps to reduce stray
inductance, and hence increases efficiency.
•
FEATURES
• Integrated Gen III MOSFETs and DrMOS
compliant gate driver IC
• Enables V
core
switching at 1 MHz
• Easily achieve > 90 % efficiency in multi-phase,
low output voltage solutions
• Low ringing on the VSWH pin reduces EMI
• Pin compatible with DrMOS 6 x 6 version 3.0
• Tri-state PWM input function prevents negative output
voltage swing
• 5 V logic levels on PWM
• MOSFET threshold voltage optimized for 5 V driver bias
supply
• Automatic skip mode operation (SMOD) for light load
efficiency
• Under-voltage lockout
• Built-in bootstrap schottky diode
• Adaptive deadtime and shoot through protection
• Thermal shutdown warning flag
• Low profile, thermally enhanced PowerPAK
®
MLP 6 x 6
40 pin package
• Halogen-free according to IEC 61249-2-21 definition
•
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• CPU and GPU core voltage regulation
• Server, computer, workstation, game console, graphics
boards, PC
SiC769CD APPLICATION DIAGRAMM
5
V
VDRV
GH
V
IN
V
IN
V
CIN
SMOD
Gate Driver
DSBL#
PWM
PWM
THDN
Controller
BOOT
V
SWH
PHASE
V
O
SiC769CD
C
GND
P
GND
Figure 1
Document Number: 64981
S11-0975-Rev. F, 16-May-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
GL
SiC769
Vishay Siliconix
ORDERING INFORMATION
Part Number
SiC769CD-T1-E3
SiC769DB
Package
PowerPAK MLP66-40
Reference board
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
Parameter
Input Voltage
Switch Node Voltage (DC)
Drive Input Voltage
Control Input Voltage
Logic Pins
Boot Voltage DC (referenced to C
GND
)
Boot Voltage < 200 ns Transient (referenced to C
GND
)
Boot to Phase Voltage DC
Boot to Phase Voltage < 200 ns
Ambient Temperature Range
Maximum Junction Temperature
Storage Junction Temperature
Soldering Peak Temperature
Note:
a. T
A
= 25 °C and all voltages referenced to P
GND
= C
GND
unless otherwise noted.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
Symbol
V
IN
V
SW
V
DRV
V
CIN
V
PWM
, V
DSBL#
,
V
THDN
, V
SMOD
V
BS
V
BS_PH
T
A
T
J
T
STG
- 65
Min.
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 40
Max.
20
20
7
7
V
CIN
+ 0.3
27
29
7
9
125
150
150
260
°C
V
Unit
RECOMMENDED OPERATING CONDITIONS
Parameter
Input Voltage
Control Input Voltage
Drive Input Voltage
Switch Node
Symbol
V
IN
V
CIN
V
DRV
V
SW_DC
Min.
3
4.5
4.5
12
Typ.
12
Max.
16
5.5
5.5
16
V
Unit
Note:
a. Recommended operating conditions are specified over the entire temperature range, and all voltages referenced to P
GND
= C
GND
unless
otherwise noted.
THERMAL RESISTANCE RATINGS
Parameter
Maximum Power Dissipation at T
PCB
= 25 °C
Maximum Power Dissipation at T
PCB
= 100 °C
Thermal Resistance from Junction to Top
Thermal Resistance from Junction to PCB
Symbol
P
D_25C
P
D_100C
R
th_J_TOP
R
th_J_PCB
Typ.
Max.
25
10
15
5
Unit
W
°C/W
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Document Number: 64981
S11-0975-Rev. F, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC769
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Test Conditions Unless Specified
V
DSBL#
= V
SMOD
= 5 V,
V
IN
= 12 V, V
VDRV
= V
VCIN
5 V,
T
A
= 25 °C
V
DSBL#
= 0 V, no switching
V
CIN
Control Input Current
I
VCIN
V
DSBL#
= 5 V, no switching
V
DSBL#
= 5 V, f
s
= 300 kHz, D = 0.1
Drive Input Current (Dynamic)
Bootstrap Supply
Bootstrap Switch Forward Voltage
Control Inputs (PWM, DSBL#, SMOD)
PWM Rising Threshold
PWM Falling Threshold
PWM Tristate Rising Threshold
PWM Tristate Falling Threshold
PWM Tristate Rising Threshold Hysteresis
PWM Tristate Falling Threshold Hysteresis
Tristate Hold-Off Time
b
PWM Input Current
SMOD, DSBL# Logic Input Voltage
Pull Down Impedance
THDN Output Low
Protection
Thermal Warning Flag Set
Thermal Warning Flag Clear
Thermal Warning Flag Hysteresis
Under Voltage Lockout
Under Voltage Lockout
Under Voltage Lockout Hysteresis
High Side Gate Discharge Resistor
b
Parameter
Power Supplies
Symbol
Min.
Typ.
a
20
400
600
11
40
0.60
Max.
Unit
µA
16
54
0.75
4.2
1.2
1.8
4.0
mV
ns
µA
V
V
V
I
VDRV
f
s
= 300 kHz, D = 0.1
f
s
= 1000 kHz, D = 0.1
V
VCIN
= 5 V, forward bias current 2 mA
3.5
0.8
0.9
3.4
mA
V
BS Diode
V
th_pwm_r
V
th_pwm_f
V
th_tri_r
V
th_tri_f
V
hys_tri_r
V
hys_tri_f
t
TSHO
I
PWM
V
LOGIC_LH
V
LOGIC_LH
R
THDN
V
THDNL
V
3.8
1.0
1.3
3.7
200
300
150
V
PWM
= 5 V
V
PWM
= 0 V
Rising (low to high)
Falling (high to low)
5 k resistor pull-up to V
CIN
2
250
- 250
0.8
40
0.04
150
135
15
°C
3.9
V
UVLO
V
UVLO_HYST
R
HS_DSCRG
Rising, on threshold
Falling, off threshold
V
VDRV
= V
VCIN
= 0 V; V
IN
= 12 V
2.5
3.3
2.9
400
20.2
V
mV
k
Notes:
a. Typical limits are established by characterization and are not production tested.
b. Guaranteed by design.
Document Number: 64981
S11-0975-Rev. F, 16-May-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC769
Vishay Siliconix
MOSFET SPECIFICATIONS
Test Conditions Unless Specified
V
VCIN
= V
DSBL#
= 5 V,
V
VIN
= 12 V, T
A
= 25 °C
V
GS
= 0, I
DS
= 250 µA
V
GH
= 5 V, resistance measured
at package pins
V
GS
= 0, I
DS
= 250 µA
V
GL
= 5 V, resistance measured
at package pins
20
1.7
Typ.
a
Parameter
High Side
Symbol
V
DS
R
DS(on)_H
V
DS
Min.
20
Max.
Unit
V
6
m
V
m
Low Side
R
DS(on)_L
Note:
a. Typical MOSFET Parameters are provided as a design guide.
TIMING SPECIFICATIONS
Test Conditions Unless Specified
V
VDRV
= V
VCIN
= V
DSBL#
= 5 V,
V
VIN
= 12 V, T
A
= 25 °C
25 % of PWM to 90 % of GH
10 % to 90 % of GH
90 % to 10 % of GH
75 % of PWM to 90 % of GL
10 % to 90 % of GL
90 % to 10 % of GL
10 % of GL to 10 % of GH
10 % of GH to 10 % of GL
10
Parameter
Turn Off Propagation Delay
High Side
a
Rise Time High Side
Fall Time High Side
Turn Off Propagation Delay
Low Side
a
Rise Time Low Side
Fall Time Low Side
Dead Time Rising
Dead Time Falling
Symbol
t
d_on_HS
t
r_HS
t
f_HS
t
d_off_LS
t
r_LS
t
f_LS
t
dead_on
t
dead_off
Min.
10
Typ.
20
8
8
20
8
8
15
15
Max.
30
Unit
30
ns
Note:
a. Min. and Max. are not 100 % production tested.
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Document Number: 64981
S11-0975-Rev. F, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC769
Vishay Siliconix
TIMING DEFINITIONS
PWM
75
%
25
%
GH
90
%
GL
10
%
SW
10
%
90
%
1 2 3 4
5 6
7
8
Region
1
2
3
4
5
6
7
8
Definition
Turn off propagation delay LS
Fall time LS
Dead time rising
Rise time HS
Turn off propagation delay HS
Fall time HS
Dead time falling
Rise time LS
Symbol
t
d_off_LS
t
f_LS
t
dead_on
t
r_HS
t
d_off_HS
t
f_HS
t
dead_off
t
r_LS
Note:
GH is referenced to the high side source. GL is referenced to the low side source.
SiC769CD BLOCK DIAGRAM
THDN
THDN
V
DRV
VDRV
BOOT
BOOT
GH
GH
Thermal
Thermal Monitor
Monitor &
Warning
and
Warning
VIN
V
IN
V
CIN
VCIN
DSBL#
DSBL#
UVLO
UVLO
20K
20K
V
CIN
VCIN
PWM
Logic
PWM Logic
Control &
Control
State Machine
and State
Machine
Anti-
Cross-
Anti-Cross-
Conduction
Conduction
Control Logic
Control
Logic
-
-
+
+
VSWH
VSWH
Vref = 1V
V
REF
= 1
V
-
-
+
+
LG
PWM
PWM
LG
V
DRV
VDRV
Vref = 1V
V
REF
= 1
V
CGND
C
GND
Zero-Current
Dectect
Zero-
Current
Detect
-
-
+
+
SMOD#
SMOD#
VSWH
PGND
VSWH
P
GND
GL
PGND
P
GND
GL
Figure 2
Document Number: 64981
S11-0975-Rev. F, 16-May-11
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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