EM351/EM357
High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
Features
-
32-bit ARM® Cortex -M3 processor
-
2.4 GHz IEEE 802.15.4-2003 transceiver & lower MAC
-
128 or 192 kB flash, with optional read protection
-
12 kB RAM memory
-
AES128 encryption accelerator
-
Flexible ADC, UART/SPI/TWI serial communications,
and general purpose timers
-
24 highly configurable GPIOs with Schmitt trigger inputs
Exceptional RF Performance
-
Normal mode link budget up to 103 dB; configurable up
to 110 dB
-
–100 dBm normal RX sensitivity; configurable to
–102 dBm (1% PER, 20 byte packet)
-
+3 dB normal mode output power; configurable up to
+8 dBm
-
Robust Wi-Fi and Bluetooth coexistence
Industry-leading ARM® Cortex -M3 processor
-
Leading 32-bit processing performance
-
Highly efficient Thumb-2 instruction set
-
Operation at 6, 12, or 24 MHz
-
Flexible Nested Vectored Interrupt Controller
Low power consumption, advanced management
-
RX Current (w/ CPU): 26 mA
-
TX Current (w/ CPU, +3 dBm TX): 31 mA
-
Low deep sleep current, with retained RAM and GPIO:
400 nA without/800 nA with sleep timer
-
Low-frequency internal RC oscillator for low-power sleep
timing
-
High-frequency internal RC oscillator for fast (110 µs)
processor start-up from sleep
Innovative network and processor debug
-
Packet Trace Port for non-intrusive packet trace with
Ember development tools
-
Serial Wire/JTAG interface
-
Standard ARM debug capabilities: Flash Patch & Break-
point; Data Watchpoint & Trace; Instrumentation Trace
Macrocell
Application Flexibility
-
Single voltage operation: 2.1–3.6 V with internal 1.8 and
-
-
-
-
1.25 V regulators
Optional 32.768 kHz crystal for higher timer accuracy
Low external component count with single 24 MHz
crystal
Support for external power amplifier
Small 7x7 mm 48-pin QFN package
PA select
TX_ACTIVE
RF_TX_ALT_P,N
PA
SYNTH
PA
DAC
MAC
+
Baseband
Data
RAM
12 kB
Program
Flash
128/192 kB
RF_P,N
LNA
IF
ADC
ARM
®
Cortex
TM
-M3
CPU with NVIC
and MPU
2
nd
level
Interrupt
controller
Bias
Packet Trace
OSCA
OSCB
VDD_CORE
VREG_OUT
nRESET
HF crystal
OSC
1.25V
Regulator
1.8V
Regulator
POR
LF crystal
OSC
Internal HF
RC-OSC
Calibration
ADC
General
purpose
timers
GPIO
registers
CPU debug
TPIU/ITM/
FPB/DWT
Always
Powered
Domain
Watchdog
Encryption
acclerator
General
Purpose
ADC
Internal LF
RC-OSC
Serial
Wire and
JTAG
debug
SWCLK,
JTCK
UART/
SPI/TWI
Chip
manager
Sleep
timer
GPIO multiplexor switch
PA[7:0], PB[7:0], PC[7:0]
Rev 1.3 8/13
Copyright © 2013 by Silicon Laboratories
EM351/EM357
Ta b l e o f C o n t e n ts
1. Typical Application ..............................................................................................................5
2. Electrical Specifications......................................................................................................8
2.1. Absolute Maximum Ratings............................................................................................8
2.2. Recommended Operating Conditions ............................................................................8
2.3. Environmental Characteristics........................................................................................9
2.4. DC Electrical Characteristics..........................................................................................9
2.5. Digital I/O Specifications .............................................................................................. 14
2.6. Non-RF System Electrical Characteristics ................................................................... 15
2.7. RF Electrical Characteristics ........................................................................................ 16
3. Functional Description ...................................................................................................... 22
4. Radio Module ..................................................................................................................... 25
4.1. Receive (RX) Path........................................................................................................25
4.2. Transmit (TX) Path ....................................................................................................... 25
4.3. Calibration .................................................................................................................... 25
4.4. Integrated MAC Module ............................................................................................... 26
4.5. Packet Trace Interface (PTI) ........................................................................................ 26
4.6. Random Number Generator......................................................................................... 26
5. ARM® Cortex™-M3 and Memory Modules ...................................................................... 27
5.1. ARM® Cortex™-M3 Microprocessor............................................................................27
5.2. Embedded Memory ...................................................................................................... 27
5.3. Memory Protection Unit................................................................................................ 34
6. System Modules.................................................................................................................35
6.1. Power Domains ............................................................................................................ 36
6.2. Resets .......................................................................................................................... 37
6.3. Clocks........................................................................................................................... 40
6.4. System Timers ............................................................................................................. 45
6.5. Power Management ..................................................................................................... 46
6.6. Security Accelerator ..................................................................................................... 49
7. GPIO (General Purpose Input/Output) ............................................................................. 50
7.1. GPIO Ports ................................................................................................................... 51
7.2. Configuration ................................................................................................................ 51
7.3. Forced Functions.......................................................................................................... 52
7.4. Reset ............................................................................................................................ 53
7.5. Boot Configuration........................................................................................................53
7.6. GPIO Modes................................................................................................................. 54
7.7. Wake Monitoring .......................................................................................................... 55
7.8. External Interrupts ........................................................................................................55
7.9. Debug Control and Status ............................................................................................ 56
7.10.GPIO Signal Assignment Summary............................................................................. 57
7.11.Registers......................................................................................................................58
8. Serial Controllers ...............................................................................................................70
8.1. Overview ......................................................................................................................70
8.2. Configuration ................................................................................................................ 71
8.3. SPI - Master Mode ....................................................................................................... 76
Rev 1.3
3
8.4. SPI - Slave Mode ......................................................................................................... 84
8.5. TWI - Two Wire serial Interfaces .................................................................................. 87
8.6. UART - Universal Asynchronous Receiver / Transmitter ............................................. 93
8.7. DMA Channels ........................................................................................................... 101
9. General Purpose Timers (TIM1 and TIM2) ..................................................................... 114
9.1. Introduction................................................................................................................. 114
9.2. GPIO Usage ............................................................................................................... 116
9.3. Timer Functional Description...................................................................................... 116
9.4. Interrupts ....................................................................................................................144
9.5. Registers ....................................................................................................................145
10. ADC (Analog to Digital Converter) .................................................................................172
10.1.Setup and Configuration ............................................................................................ 173
10.2.Interrupts....................................................................................................................176
10.3.Operation ................................................................................................................... 177
10.4.Calibration.................................................................................................................. 178
10.5.ADC Key Parameters................................................................................................. 179
10.6.Registers....................................................................................................................183
11. Interrupt System .............................................................................................................. 190
11.1.Nested Vectored Interrupt Controller (NVIC) ............................................................. 190
11.2.Event Manager........................................................................................................... 192
11.3.Non-Maskable Interrupt (NMI) ................................................................................... 195
11.4.Faults .........................................................................................................................195
11.5.Registers....................................................................................................................196
12. Trace Port Interface Unit (TPIU)...................................................................................... 203
13. Instrumentation Trace Macrocell (ITM) ..........................................................................204
14. Data Watchpoint and Trace (DWT) .................................................................................205
15. Flash Patch and Breakpoint (FPB) .................................................................................206
16. Integrated Voltage Regulator.......................................................................................... 207
17. Serial Wire and JTAG (SWJ) Interface ........................................................................... 209
18. Ordering Information ....................................................................................................... 210
19. Pin Definitions.................................................................................................................. 211
19.1.Pin Definitions ............................................................................................................ 211
20. Package ............................................................................................................................ 223
20.1.QFN48 Footprint Recommendations ......................................................................... 223
20.2.Solder Temperature Profile........................................................................................225
21. Top Marking...................................................................................................................... 227
22. Shipping Box Label ......................................................................................................... 228
Appendix A—Register Address Table.................................................................................229
Appendix B—Abbreviations and Acronyms....................................................................... 235
Appendix C—References ..................................................................................................... 239
Document Change List ......................................................................................................... 240
Contact Information .............................................................................................................. 241
4
Rev 1.3
1. Typical Application
Figure 1.1 illustrates the typical application circuit, and Table 1.1 contains an example bill of materials (BOM) for
the off-chip components required by the EM35x.
Note:
The circuit shown in
Figure 1.1
is for example purposes only, and the BOM is for budgetary quotes only. For a complete
reference design, please download one of the latest Ember Hardware Reference Designs from the Silicon Labs website
(www.silabs.com/zigbee-support).
The Balun provides an impedance transformation from the antenna to the EM35x for both TX and RX modes.
L1 tunes the impedance presented to the RF port for maximum transmit power and receive sensitivity.
The harmonic filter (L2, L3, C5, C6 and C9) provides additional suppression of the second harmonic, which
increases the margin over the FCC limit.
The 24 MHz crystal Y1 with loading capacitors is required and provides the high-frequency crystal oscillator source
for the EM35x's main system clock. The 32.768 kHz crystal with loading capacitors generates a highly accurate
low-frequency crystal oscillator for use with peripherals, but it is not mandatory as the low-frequency internal RC
oscillator can be used.
Loading capacitance and ESR (C1 and R3) provides stability for the internal 1.8 V regulator.
Loading capacitance C2 provides stability for the internal 1.25 V regulator, no ESR is required because it is
contained within the chip.
Resistor R1 reduces the operating voltage of the flash memory, this reduces current consumption and improves
sensitivity by 1 dB when compared to not using it.
Various decoupling capacitors are required, these should be placed as close to their corresponding pins as
possible. For values and locations see one of the latest reference designs.
An antenna matched to 50
is required.
Rev 1.3
5
FPGA/CPLD
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